公开(公告)号：US20140086070A1

公开(公告)日：2014-03-27

申请号：US13625416

申请日：2012-09-24

申请人： Gurjeet S. Saund ,  James B. Keller ,  Manu Gulati ,  Sukalpa Biswas

发明人： Gurjeet S. Saund ,  James B. Keller ,  Manu Gulati ,  Sukalpa Biswas

IPC分类号： H04L12/26

CPC分类号： G06F13/1605 ,  Y02D10/14

摘要： In some embodiments, a system includes a shared, high bandwidth resource (e.g. a memory system), multiple agents configured to communicate with the shared resource, and a communication fabric coupling the multiple agents to the shared resource. The communication fabric may be equipped with limiters configured to limit bandwidth from the various agents based on one or more performance metrics measured with respect to the shared, high bandwidth resource. For example, the performance metrics may include one or more of latency, number of outstanding transactions, resource utilization, etc. The limiters may dynamically modify their limit configurations based on the performance metrics. In an embodiment, the system may include multiple thresholds for the performance metrics, and exceeding a given threshold may include modifying the limiters in the communication fabric. There may be hysteresis implemented in the system as well in some embodiments, to reduce the frequency of transitions between configurations.

摘要翻译： 在一些实施例中，系统包括共享的高带宽资源（例如，存储器系统），被配置为与共享资源通信的多个代理以及将多个代理耦合到共享资源的通信结构。 通信结构可以配备有限制器，其被配置为基于针对共享的高带宽资源测量的一个或多个性能度量来限制来自各种代理的带宽。 例如，性能度量可以包括延迟，未决事务数量，资源利用等中的一个或多个。限制器可以基于性能度量动态修改其限制配置。 在一个实施例中，系统可以包括用于性能度量的多个阈值，并且超过给定阈值可以包括修改通信结构中的限制器。 在一些实施例中，也可能在系统中实现滞后，以减少配置之间的转换频率。

公开(公告)号：US07609718B2

公开(公告)日：2009-10-27

申请号：US10356661

申请日：2003-01-31

申请人： Manu Gulati ,  Laurent Moll ,  Barton Sano

发明人： Manu Gulati ,  Laurent Moll ,  Barton Sano

IPC分类号： H04J3/16

CPC分类号： H04L12/56

摘要： A multiple processor device generates a control packet for at least one connectionless-based packet in partial accordance with a control packet format of the connection-based point-to-point link and partially not in accordance with the control packet format. For instance, the multiple processor device generates the control packet to include, in noncompliance with the control packet format, one or more of an indication that at least one connectionless-based packet is being transported, an indication of a virtual channel of a plurality of virtual channels associated with the at least one connectionless-based packet, an indication of an amount of data included in the associated data packet, status of the at least one connectionless-based packet, and an error status indication. The multiple processor device then generates the associated data packet in accordance with a data packet format of the connection-based point-to-point link, wherein the data packet includes at least a portion of the at least one connectionless-based packet.

摘要翻译： 多处理器设备部分地根据基于连接的点对点链路的控制分组格式生成用于至少一个基于无连接的分组的控制分组，并且部分地不符合控制分组格式。 例如，多处理器设备生成控制分组，以在不遵守控制分组格式的情况下包括以下指示：至少一个基于无连接的分组正被传输的指示，多个 与至少一个基于无连接的分组关联的虚拟频道，包括在相关数据分组中的数据量的指示，至少一个基于无连接的分组的状态以及错误状态指示。 然后，多处理器设备根据基于连接的点对点链路的数据分组格式生成相关联的数据分组，其中数据分组包括至少一个基于无连接的分组的至少一部分。

公开(公告)号：US07403525B2

公开(公告)日：2008-07-22

申请号：US10356323

申请日：2003-01-31

申请人： Barton Sano ,  Laurent Moll ,  Manu Gulati

发明人： Barton Sano ,  Laurent Moll ,  Manu Gulati

IPC分类号： H04L12/56

CPC分类号： H04L45/38 ,  H04L49/25

摘要： According to the present invention, the multiple processor device determines routing for a plurality of data segments. In determining the routing, the multiple processor device first receives the plurality of data segments. The plurality of data segments include multiplexed data fragments from at least one of a plurality of virtual channels. Further, a data segment of the plurality of data segments corresponds to one of the multiplexed data fragments. The multiple processor device then applies at least one routing rule to one of the plurality of data segments to produce at least one result corresponding to the one of the plurality of data segments. The multiple processor device then interprets the at least one result to determine whether sufficient information is available to render a routing decision for the one of the plurality of data segments. When the multiple processor device determines that there is sufficient information to render a routing decision, the multiple processor device determines routing of the one of the plurality of data segments. When there is insufficient information to render a routing decision, the one of the plurality of data segments is stored in a buffer corresponding to a packet in which the one of the plurality of data segments was received. These operations are repeated for subsequent data segments.

摘要翻译： 根据本发明，多处理器设备确定多个数据段的路由。 在确定路由时，多处理器设备首先接收多个数据段。 多个数据段包括来自多个虚拟通道中的至少一个的多路复用数据片段。 此外，多个数据段的数据段对应于多路复用数据段中的一个。 多处理器设备然后将至少一个路由规则应用于多个数据段中的一个，以产生与多个数据段中的一个对应的至少一个结果。 多处理器设备然后解释至少一个结果以确定足够的信息是否可用于为多个数据段中的一个数据段呈现路由决定。 当多处理器设备确定有足够的信息来呈现路由决定时，多处理器设备确定该多个数据段之一的路由。 当没有足够的信息来呈现路由决定时，多个数据段中的一个数据段被存储在与其中接收多个数据段中的一个数据段的分组相对应的缓冲器中。 对后续数据段重复这些操作。

公开(公告)号：US20050147105A1

公开(公告)日：2005-07-07

申请号：US11069313

申请日：2005-03-01

申请人： Barton Sano ,  Koray Oner ,  Laurent Moll ,  Manu Gulati

发明人： Barton Sano ,  Koray Oner ,  Laurent Moll ,  Manu Gulati

IPC分类号： G06F13/28 ,  H04L12/56

CPC分类号： H04L49/10 ,  H04L49/602

摘要： An apparatus includes a first interface circuit, a second interface circuit, a memory controller for configured to interface to a memory, and a packet DMA circuit. The first interface circuit is configured to couple to a first interface for receiving and transmitting packet data. Similarly, the second interface circuit is configured to couple to a second interface for receiving and transmitting packet data. The packet DMA circuit is coupled to receive a first packet from the first interface circuit and a second packet from the second interface circuit. The packet DMA circuit is configured to transmit the first packet and the second packet in write commands to the memory controller to be written to the memory. In some embodiments, a switch is coupled to the first interface circuit, the second interface circuit, and the packet DMA circuit.

公开(公告)号：US06175911B1

公开(公告)日：2001-01-16

申请号：US09137583

申请日：1998-08-21

申请人： Stuart Oberman ,  Stephan G. Meier ,  Manu Gulati

发明人： Stuart Oberman ,  Stephan G. Meier ,  Manu Gulati

IPC分类号： G06F9302

CPC分类号： G06F7/57 ,  G06F7/535 ,  G06F7/5525 ,  G06F2207/3884

摘要： A multiplier capable of performing complex iterative calculations such as division and square root concurrently with simple independent multiplication operations is disclosed. The division and square root operations are performed using iterative multiplication operations such as the Newton Raphson iteration and series expansion. These iterative calculations may require a number of passes through the multiplier. Since the multiplier may be pipelined, it may experience a number of idle cycles during the iterative calculations. The multiplier is configured to utilize these idle cycles to perform independent simple multiplication operations. The multiplier may be configured to assert a control signal that is indicative of future idle cycles in the first stages of the multiplier pipeline. The control signal may be used by control logic to dispatch independent simple multiplication operations to the multiplier for execution during the idle clock cycles. The multiplier may also be configured to concurrently execute two independent iterative operations.

摘要翻译： 公开了能够与简单的独立乘法运算同时执行复数迭代计算（例如除法和平方根）的乘法器。 使用诸如牛顿拉夫逊迭代和序列扩展的迭代乘法运算进行除法和平方根运算。 这些迭代计算可能需要通过乘数的多次通过。 由于乘法器可能被流水线化，所以在迭代计算期间可能会遇到多个空闲周期。 乘法器被配置为利用这些空闲周期来执行独立的简单乘法运算。 乘法器可以被配置为断定指示乘法器管线的第一级中的将来的空闲周期的控制信号。 控制信号可以由控制逻辑用于将独立的简单乘法运算发送到乘法器，以在空闲时钟周期期间执行。 乘法器还可以被配置为同时执行两个独立的迭代操作。

公开(公告)号：US08848577B2

公开(公告)日：2014-09-30

申请号：US13625416

申请日：2012-09-24

申请人： Gurjeet S. Saund ,  James B. Keller ,  Manu Gulati ,  Sukalpa Biswas

发明人： Gurjeet S. Saund ,  James B. Keller ,  Manu Gulati ,  Sukalpa Biswas

IPC分类号： H04L12/28

CPC分类号： G06F13/1605 ,  Y02D10/14

摘要： In some embodiments, a system includes a shared, high bandwidth resource (e.g. a memory system), multiple agents configured to communicate with the shared resource, and a communication fabric coupling the multiple agents to the shared resource. The communication fabric may be equipped with limiters configured to limit bandwidth from the various agents based on one or more performance metrics measured with respect to the shared, high bandwidth resource. For example, the performance metrics may include one or more of latency, number of outstanding transactions, resource utilization, etc. The limiters may dynamically modify their limit configurations based on the performance metrics. In an embodiment, the system may include multiple thresholds for the performance metrics, and exceeding a given threshold may include modifying the limiters in the communication fabric. There may be hysteresis implemented in the system as well in some embodiments, to reduce the frequency of transitions between configurations.

摘要翻译： 在一些实施例中，系统包括共享的高带宽资源（例如，存储器系统），被配置为与共享资源通信的多个代理以及将多个代理耦合到共享资源的通信结构。 通信结构可以配备有限制器，其被配置为基于针对共享的高带宽资源测量的一个或多个性能度量来限制来自各种代理的带宽。 例如，性能度量可以包括延迟，未决事务数量，资源利用等中的一个或多个。限制器可以基于性能度量动态修改其限制配置。 在一个实施例中，系统可以包括用于性能度量的多个阈值，并且超过给定阈值可以包括修改通信结构中的限制器。 在一些实施例中，也可能在系统中实现滞后，以减少配置之间的转换频率。

公开(公告)号：US08799715B2

公开(公告)日：2014-08-05

申请号：US13533295

申请日：2012-06-26

申请人： Manu Gulati ,  James D. Ramsay ,  Erik P. Machnicki ,  Jianlin Yu

发明人： Manu Gulati ,  James D. Ramsay ,  Erik P. Machnicki ,  Jianlin Yu

IPC分类号： G06F11/00

CPC分类号： G06F11/27

摘要： In one embodiment, an SOC includes multiple components including a CPU complex and one or more non-CPU components such as peripheral interface controllers, memory controllers, media components, etc. The SOC also includes an SOC debug control unit, which is coupled to receive detected debug events from the components. Each component may include a local debug control unit that is configured to monitor for various debug events within that component. The debug events may be specific to the component. The local debug control units may transmit detected events to the SOC debug control unit. The SOC debug control unit may detect one or more events from one or more components, and may halt the components of the SOC responsive to detecting the selected events.

摘要翻译： 在一个实施例中，SOC包括多个组件，包括CPU复合体和一个或多个非CPU组件，例如外围接口控制器，存储器控制器，媒体组件等.SAC还包括SOC调试控制单元，其被耦合以接收 从组件检测到调试事件。 每个组件可以包括本地调试控制单元，其被配置为监视该组件内的各种调试事件。 调试事件可能是组件特有的。 本地调试控制单元可以将检测到的事件发送到SOC调试控制单元。 SOC调试控制单元可以从一个或多个组件检测一个或多个事件，并且可以响应于检测所选择的事件而停止SOC的组件。

公开(公告)号：US20140052930A1

公开(公告)日：2014-02-20

申请号：US13590159

申请日：2012-08-20

申请人： Manu Gulati ,  James D. Ramsay ,  Kevin R. Walker

发明人： Manu Gulati ,  James D. Ramsay ,  Kevin R. Walker

IPC分类号： G06F12/08 ,  G06F11/22

CPC分类号： G06F11/22 ,  G06F11/3013 ,  G06F11/3476 ,  G06F11/348 ,  G06F11/349 ,  G06F11/3636 ,  G06F11/366 ,  G06F12/084 ,  G06F2201/805 ,  Y02D10/13 ,  Y02D10/34

摘要： A system and method for efficiently storing traces of multiple components in an embedded system. A system-on-a-chip (SOC) includes a trace unit for collecting and storing trace history, bus event statistics, or both. The SOC may transfer cache coherent messages across multiple buses between a shared memory and a cache coherent controller. The trace unit includes a trace buffer with multiple physical partitions assigned to subsets of the multiple buses. The number of partitions is less than the number of multiple buses. One or more trace instructions may cause a trace history, trace bus event statistics, local time stamps and a global time-base value to be stored in a physical partition within the trace buffer.

摘要翻译： 一种用于在嵌入式系统中高效存储多个组件的轨迹的系统和方法。 系统级芯片（SOC）包括用于收集和存储跟踪历史，总线事件统计信息或两者的跟踪单元。 SOC可以在共享存储器和高速缓存一致控制器之间的多个总线上传送高速缓存相干消息。 跟踪单元包括具有分配给多个总线的子集的多个物理分区的跟踪缓冲器。 分区的数量少于多个总线的数量。 一个或多个跟踪指令可能会导致跟踪历史记录，跟踪总线事件统计信息，本地时间戳和全局时基值存储在跟踪缓冲区中的物理分区中。

公开(公告)号：US08571033B2

公开(公告)日：2013-10-29

申请号：US13088341

申请日：2011-04-16

申请人： Manu Gulati

发明人： Manu Gulati

IPC分类号： H04L12/56

CPC分类号： H04L49/252

摘要： Smart routing between peers in a point-to-point link based system begins when a device of a plurality of devices in a point-to-point link interconnected system receives a packet from an upstream link or a downstream link. The processing continues when the device interprets the packet to determine a destination of the packet. If the device is the destination of the packet, the device accepts the packet. If, however, the device is not the destination of the packet, the device forwards the packet on another upstream link or another downstream link without alteration of at least one of: source information of the packet and destination information of the packet.

公开(公告)号：US20130227245A1

公开(公告)日：2013-08-29

申请号：US13406905

申请日：2012-02-28

申请人： Rohit K. Gupta ,  Manu Gulati

发明人： Rohit K. Gupta ,  Manu Gulati

IPC分类号： G06F12/10

CPC分类号： G06F12/1027 ,  G06F2212/6028 ,  G06F2212/654

摘要： Techniques are disclosed relating to integrated circuits that implement a virtual memory. In one embodiment, an integrated circuit is disclosed that includes a translation lookaside buffer configured to store non-prefetched translations and a translation table configured to store prefetched translations. In such an embodiment, the translation lookaside buffer and the translation table share table walk circuitry. In some embodiments, the table walk circuitry is configured to store a translation in the translation table in response to a prefetch request and without updating the translation lookaside buffer. In some embodiments, the translation lookaside buffer, the translation table, and table walk circuitry are included within a memory management unit configured to service memory requests received from a plurality of client circuits via a plurality of direct memory access (DMA) channels.

摘要翻译： 公开了涉及实现虚拟存储器的集成电路的技术。 在一个实施例中，公开了一种集成电路，其包括被配置为存储非预取的翻译的翻译后备缓冲器和被配置为存储预取的翻译的翻译表。 在这样的实施例中，翻译后备缓冲器和翻译表共享表行走电路。 在一些实施例中，表走路电路被配置为响应于预取请求而在转换表中存储转换，并且不更新转换后备缓冲器。 在一些实施例中，翻译后备缓冲器，转换表和行走电路被包括在存储器管理单元内，该存储器管理单元经配置以经由多个直接存储器访问（DMA）通道来服务从多个客户端电路接收的存储器请求。