公开(公告)号：US07669028B2

公开(公告)日：2010-02-23

申请号：US11348884

申请日：2006-02-07

申请人： Mark D. Bellows ,  Brian M. McKevett ,  Tolga Ozguner

发明人： Mark D. Bellows ,  Brian M. McKevett ,  Tolga Ozguner

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F13/1689

摘要： Embodiments of the present invention optimize data bandwidth across an asynchronous buffer in a system with a variable clock domain. A move signal may be asserted to transfer data associated with a command into the asynchronous buffer. After the data has been moved into the buffer, an acknowledge signal may indicate that the transfer is complete. A launch signal may transfer the data in the asynchronous buffer to memory. Embodiments of the present invention allow the processing of a next command to begin at the earliest possible time while data associated with a previous command is being transferred into and out of the buffer, thereby increasing throughput and improving performance.

摘要翻译： 本发明的实施例通过具有可变时钟域的系统中的异步缓冲器来优化数据带宽。 可以断言移动信号将与命令相关联的数据传送到异步缓冲器。 数据移入缓冲区后，确认信号可能表示传输完成。 发射信号可以将异步缓冲器中的数据传输到存储器。 本发明的实施例允许下一个命令的处理在尽可能早的时间开始，而与先前命令相关联的数据正被传入和传出缓冲器，从而提高吞吐量并提高性能。

公开(公告)号：US20080063009A1

公开(公告)日：2008-03-13

申请号：US11934810

申请日：2007-11-05

申请人： Kerry Imming ,  John Irish ,  Joseph Logan ,  Tolga Ozguner ,  Michael Siegel

发明人： Kerry Imming ,  John Irish ,  Joseph Logan ,  Tolga Ozguner ,  Michael Siegel

IPC分类号： H04J3/16

CPC分类号： H04L49/901 ,  H04L49/90

摘要： A method, apparatus and computer program product are provided for implementing a pointer and stake model for frame alteration code in a network processor. A current pointer and a stake are provided for a packet selected for transmit. The current pointer is maintained for tracking a current position for frame alteration operations in the packet. The stake is maintained for tracking a start of a current header for frame alteration operations in the packet. The current pointer is used by frame alteration code instructions to specify a sequence of operations relative to the current pointer. The specified frame alteration sequence is compact in terms of code size to operate on data within a small window of bytes. Advance pointer instructions allow the current and stake pointers to be advanced an arbitrary number of bytes into the packet.

摘要翻译： 提供了一种方法，装置和计算机程序产品，用于在网络处理器中实现用于帧改变码的指针和拍摄模型。 为选择用于发送的分组提供当前指针和分支。 保持当前指针用于跟踪分组中帧更改操作的当前位置。 保留该批次用于跟踪该分组中的帧更改操作的当前报头的开始。 当前指针由帧改变代码指令使用以指定相对于当前指针的操作序列。 指定的帧改变序列在代码大小方面是紧凑的，以便在小的字节窗口内对数据进行操作。 高级指针指令允许当前和指针指针以任意数量的字节进入数据包。

公开(公告)号：US20080040534A1

公开(公告)日：2008-02-14

申请号：US11875469

申请日：2007-10-19

申请人： Mark Bellows ,  Kent Haselhorst ,  Paul Ganfield ,  Tolga Ozguner

发明人： Mark Bellows ,  Kent Haselhorst ,  Paul Ganfield ,  Tolga Ozguner

IPC分类号： G06F12/00

CPC分类号： G11C29/02 ,  G11C29/022 ,  G11C29/028

摘要： A method, an apparatus, and a computer program are provided to reuse functional data buffers. With Extreme Data Rate (XDR™) Dynamic Random Access Memory (DRAM), test patterns are employed to dynamically calibrate data with the clock. To perform this task, data buffers are employed to store data and commands for the calibration patterns. However, there are different procedures and requirements for transmission and reception calibrations. Hence, to reduce the amount of hardware needed to perform transmission and reception calibrations, the data buffers employ additional front end circuitry to reuse the buffers for both tasks.

摘要翻译： 提供了一种方法，装置和计算机程序来重用功能数据缓冲器。 使用极限数据速率（XDR（TMDR））动态随机存取存储器（DRAM），采用测试模式来动态校准数据与时钟。 为了执行此任务，采用数据缓冲器来存储校准模式的数据和命令。 然而，发送和接收校准有不同的程序和要求。 因此，为了减少执行发送和接收校准所需的硬件数量，数据缓冲器使用附加的前端电路来为这两个任务重新使用缓冲器。

公开(公告)号：US07239635B2

公开(公告)日：2007-07-03

申请号：US10180993

申请日：2002-06-27

申请人： Tolga Ozguner

发明人： Tolga Ozguner

IPC分类号： H04L12/28 ,  G06F15/00 ,  G06F13/00

CPC分类号： H04L47/6225 ,  H04L47/50 ,  H04L49/90

摘要： A method and apparatus are provided for implementing frame header alterations on multiple concurrent frames. Each of a plurality of frame data alteration engines includes a pair of a command decoder and an associated data aligner. A command buffer arbiter sequentially receives frame alteration commands and sequentially selects one of the frame data alteration engines for the sequentially received frame alteration commands. Each command decoder receives and decodes frame alteration commands and provides frame alignment commands and alteration instructions and each associated data aligner receives frame data and selectively latches data bytes of the received frame data responsive to the frame alignment commands and sequentially provides an aligned frame data output of a predefined number of bytes. An alteration engine receives sequentially provided aligned frame data output and alteration instructions from a selected one the plurality of frame data alteration engines and provides sequential altered frame data responsive to the received alteration instructions.

摘要翻译： 提供了一种用于在多个并发帧上实现帧头改变的方法和装置。 多个帧数据变换引擎中的每一个包括一对命令解码器和相关联的数据对准器。 命令缓冲器仲裁器顺序地接收帧改变命令，并且顺序地选择用于顺序接收的帧改变命令的帧数据改变引擎中的一个。 每个命令解码器接收并解码帧改变命令并提供帧对准命令和改变指令，并且每个相关联的数据对准器接收帧数据，并且响应于帧对准命令选择性地锁存接收到的帧数据的数据字节，并且顺序地提供对准的帧数据输出 预定义的字节数。 改变引擎从所选择的多个帧数据变换引擎中顺序地提供对准的帧数据输出和改变指令，并响应于所接收的改变指令提供顺序改变的帧数据。

公开(公告)号：US07224701B2

公开(公告)日：2007-05-29

申请号：US10185556

申请日：2002-06-27

申请人： Tolga Ozguner

发明人： Tolga Ozguner

IPC分类号： H04J3/16 ,  H04L12/28

CPC分类号： H04L69/22

摘要： A method and apparatus are provided for implementing frame header alterations using byte-wise arithmetic logic units (ALUs). First and second stage alteration engines include a plurality of first stage byte-wise arithmetic logic units (ALUs). Each ALU includes inputs for receiving frame data, command data, register data, and commands, and register data and data outputs. The first and second stage byte-wise ALUs respectively perform the received first and second stage commands and the second stage ALUs provide altered frame data output. The commands enable operations such as load, add, and, or, move, and the like used by the two-stages of byte-wise ALUs forming the alteration engines to perform the alterations or combine new header data into a stream of frame data.

摘要翻译： 提供了一种使用字节式算术逻辑单元（ALU）来实现帧头改变的方法和装置。 第一和第二阶段改造引擎包括多个第一级字节式算术逻辑单元（ALU）。 每个ALU包括用于接收帧数据，命令数据，寄存器数据和命令以及寄存器数据和数据输出的输入。 第一级和第二级字节式ALU分别执行接收到的第一级和第二级命令，并且第二级ALU提供改变的帧数据输出。 这些命令允许形成改变引擎的两级字节ALU使用的诸如加载，添加和/或移动等操作来执行改变或将新的头部数据组合成帧数据流。

公开(公告)号：US20060174082A1

公开(公告)日：2006-08-03

申请号：US11050021

申请日：2005-02-03

申请人： Mark Bellows ,  Paul Ganfield ,  Kent Haselhorst ,  Ryan Heckendorf ,  Tolga Ozguner

发明人： Mark Bellows ,  Paul Ganfield ,  Kent Haselhorst ,  Ryan Heckendorf ,  Tolga Ozguner

IPC分类号： G06F13/28

CPC分类号： G06F13/161 ,  G06F13/1647

摘要： A method and apparatus for managing write-to-read turnarounds in an early read after write memory system are presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.

摘要翻译： 提出了一种用于在写入存储器系统之后的早期读取中管理写入到读取周转的方法和装置。 存储器控制器逻辑识别写入操作的存储体组，允许在写入操作完成之前发出不同的存储体读取操作，并且一旦写入操作完成，就允许执行相同的存储体读取操作。 存储器控制器包括操作计数器逻辑，操作选择逻辑，操作接受逻辑，命令格式化逻辑和存储器接口逻辑。 操作计数器逻辑接收来自操作接受逻辑的新操作相关信号，并且继而向操作选择逻辑和操作接受逻辑提供关于什么时候发出对应于偶数DRAM组的读操作的信​​号 一个奇怪的DRAM银行。

公开(公告)号：US06880026B2

公开(公告)日：2005-04-12

申请号：US10147615

申请日：2002-05-16

申请人： Kerry Christopher Imming ,  Christopher Jon Johnson ,  Tolga Ozguner

发明人： Kerry Christopher Imming ,  Christopher Jon Johnson ,  Tolga Ozguner

IPC分类号： G06F13/42

CPC分类号： G06F13/4273

摘要： A method and apparatus are provided for implementing chip-to-chip interconnect bus initialization. The chip-to-chip interconnect bus includes first and second unidirectional buses for full duplex communications between two chips. A lower than normal bus frequency is used during the initialization process. A transmit initialization sequencer of a source transmits predefined SYNC symbols on the connected unidirectional bus. A receive initialization sequencer of a destination chip checks for a defined number of valid SYNC or IDLE symbols. When the receive initialization sequencer of a destination detects the defined number of valid SYNC or IDLE symbols, the receive initialization sequencer triggers a transmit initialization sequencer of the destination to transmit IDLE symbols on the connected unidirectional bus. The transmitted IDLE symbols are detected by a receive initialization sequencer at the source, indicating that both ends of the interconnect bus have synchronized. Once link synchronization is established, the source transmits configuration information to the destination using normal bus messages. Programmable delay elements and configuration registers are set.

摘要翻译： 提供了一种用于实现芯片到芯片互连总线初始化的方法和装置。 芯片到芯片互连总线包括用于两芯片之间的全双工通信的第一和第二单向总线。 在初始化过程中使用低于正常总线频率。 源的发送初始化定序器在所连接的单向总线上发送预定义的SYNC符号。 目标芯片的接收初始化定序器检查定义数量的有效SYNC或IDLE符号。 当目的地的接收初始化定序器检测到有效的SYNC或IDLE符号的定义数量时，接收初始化定序器触发目的地的发送初始化定序器，以在连接的单向总线上发送空闲符号。 发送的IDLE符号由源处的接收初始化定序器检测，指示互连总线的两端同步。 一旦建立了链路同步，则源使用正常总线消息将配置信息发送到目的地。 可编程延迟元件和配置寄存器被设置。

公开(公告)号：US20050018684A1

公开(公告)日：2005-01-27

申请号：US10625954

申请日：2003-07-24

申请人： Gerald Fagerness ,  Kerry Imming ,  Brian McKevett ,  James Mikos ,  Tolga Ozguner

发明人： Gerald Fagerness ,  Kerry Imming ,  Brian McKevett ,  James Mikos ,  Tolga Ozguner

IPC分类号： H04L12/56

CPC分类号： H04L49/3009

摘要： A method is provided for address mapping in a network processor. The method includes the steps of (1) determining a port number of a port that receives a data cell; (2) determining a virtual path identifier and a virtual channel identifier for the data cell; and (3) creating a first index based on at least one of the port number, the virtual path identifier and the virtual channel identifier. The method further includes (1) accessing one of a plurality of entries stored in a first on-chip memory using the first index; (2) creating a second index based on the accessed entry of the first on-chip memory; and (3) accessing an entry of a second memory based on the second index. Numerous other aspects are provided.

摘要翻译： 提供了一种用于网络处理器中的地址映射的方法。 该方法包括以下步骤：（1）确定接收数据信元的端口的端口号; （2）确定数据信元的虚拟路径标识符和虚拟信道标识符; 以及（3）基于端口号，虚拟路径标识符和虚拟信道标识符中的至少一个来创建第一索引。 该方法还包括：（1）使用第一索引访问存储在第一片上存储器中的多个条目中的一个; （2）基于所访问的第一片上存储器的条目创建第二索引; 和（3）基于第二索引访问第二存储器的条目。 提供了许多其他方面。

公开(公告)号：US20080046632A1

公开(公告)日：2008-02-21

申请号：US11851468

申请日：2007-09-07

申请人： Mark Bellows ,  Paul Ganfield ,  Kent Haselhorst ,  Ryan Heckendorf ,  Tolga Ozguner

发明人： Mark Bellows ,  Paul Ganfield ,  Kent Haselhorst ,  Ryan Heckendorf ,  Tolga Ozguner

IPC分类号： G06F12/00

CPC分类号： G06F13/161 ,  G06F13/1647

摘要： A method and apparatus for managing write-to-read turnarounds in an early read after write memory system are presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.

摘要翻译： 提出了一种用于在写入存储器系统之后的早期读取中管理写入到读取周转的方法和装置。 存储器控制器逻辑识别写入操作的存储体组，允许在写入操作完成之前发出不同的存储体读取操作，并且一旦写入操作完成，就允许执行相同的存储体读取操作。 存储器控制器包括操作计数器逻辑，操作选择逻辑，操作接受逻辑，命令格式化逻辑和存储器接口逻辑。 操作计数器逻辑接收来自操作接受逻辑的新操作相关信号，并且继而向操作选择逻辑和操作接受逻辑提供关于什么时候发出对应于偶数DRAM组的读操作的信​​号 一个奇怪的DRAM银行。

公开(公告)号：US20070220361A1

公开(公告)日：2007-09-20

申请号：US11347415

申请日：2006-02-03

申请人： Melissa Barnum ,  Lonny Lambrecht ,  Tolga Ozguner

发明人： Melissa Barnum ,  Lonny Lambrecht ,  Tolga Ozguner

IPC分类号： G06F11/00

CPC分类号： G06F11/3636

摘要： The present invention provides a way to offload trace data from a processor and store the trace data in external memory. By accumulating trace data in large buffers and sending them to a memory interface controller, the memory interface controller may write trace data to memory as the memory interface controller would execute a normal write to memory. In this manner, no additional I/O memory pins are required and processor memory storage for trace data is kept to a minimum. Furthermore, by using a special port to the memory interface controller the writing of trace data may be accomplished in a manner that does not affect the speed of the on-chip bus between the processor and the memory interface controller.

摘要翻译： 本发明提供了一种从处理器卸载跟踪数据并将跟踪数据存储在外部存储器中的方法。 通过在大缓冲区中累积跟踪数据并将其发送到存储器接口控制器，存储器接口控制器可以将跟踪数据写入存储器，因为存储器接口控制器将执行对存储器的正常写操作。 以这种方式，不需要额外的I / O存储器引脚，并且将用于跟踪数据的处理器存储器存储保持最小。 此外，通过将特殊端口用于存储器接口控制器，跟踪数据的写入可以以不影响处理器和存储器接口控制器之间的片上总线速度的方式来实现。