公开(公告)号：US6040223A

公开(公告)日：2000-03-21

申请号：US373636

申请日：1999-08-13

申请人： Meng-Chang Liu ,  Jyh-Feng Lin ,  Ming-Shu Yen ,  Su-Ying Su ,  Fu-Ying Chiu ,  Chien-Hung Lin

发明人： Meng-Chang Liu ,  Jyh-Feng Lin ,  Ming-Shu Yen ,  Su-Ying Su ,  Fu-Ying Chiu ,  Chien-Hung Lin

IPC分类号： H01L21/336 ,  H01L21/60 ,  H01L21/768

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L29/6656 ,  H01L29/6659

摘要： A method for making improved polysilicon FET gate electrodes having composite sidewall spacers is achieved. After forming the polysilicon gate electrodes on the substrate, a SiO.sub.2 stress-release layer is deposited having a trapezoidal shape. A Si.sub.3 N.sub.4 layer is deposited and plasma etched back using the SiO.sub.2 layer as an etch-endpoint-detect layer to form composite sidewall spacers that include portions of the trapezoidal-shaped oxide layer. The SiO.sub.2 layer protects the source/drain areas from plasma etch damage that could cause high leakage currents. The Si.sub.3 N.sub.4 also extends over the SiO.sub.2 layer at the upper edges of the polysilicon gate electrodes. This prevents erosion of the SiO.sub.2 along the gate electrodes when the remaining oxide is removed from the source/drain areas using hydrofluoric acid wet etching. When an insulating layer is deposited over the FETs, and self-aligned contact openings are etched to the source/drain areas and extending over the gate electrodes, the Si.sub.3 N.sub.4 extending over the portion of the trapezoidal-shaped SiO.sub.2 layer that forms part of the composite sidewall spacer protects the SiO.sub.2 from etching. This results in more reliable contacts without degrading the FET performance.

摘要翻译： 实现了具有复合侧壁间隔物的改进的多晶硅FET栅电极的方法。 在基板上形成多晶硅栅电极之后，沉积具有梯形形状的SiO 2应力释放层。 沉积Si 3 N 4层并使用SiO 2层等离子体蚀刻回蚀刻端点检测层，以形成包括梯形氧化物层的部分的复合侧壁间隔物。 SiO 2层保护源极/漏极区域免受可能导致高漏电流的等离子体蚀刻损伤。 Si 3 N 4也在多晶硅栅电极的上边缘处在SiO 2层上延伸。 当使用氢氟酸湿蚀刻从剩余的氧化物从源极/漏极区域移除时，这防止了沿着栅电极的SiO 2的侵蚀。 当绝缘层沉积在FET上方，并且自对准接触开口被蚀刻到源极/漏极区域并且在栅电极上延伸时，Si3N4延伸超过形成复合材料的一部分的梯形SiO 2层的部分 侧壁间隔件保护SiO 2免受蚀刻。 这导致更可靠的触点，而不会降低FET性能。

公开(公告)号：US5801094A

公开(公告)日：1998-09-01

申请号：US873500

申请日：1997-06-12

申请人： Tri-Rung Yew ,  Meng-Chang Liu ,  Water Lur ,  Shih-Wei Sun

发明人： Tri-Rung Yew ,  Meng-Chang Liu ,  Water Lur ,  Shih-Wei Sun

IPC分类号： H01L21/768 ,  H01L21/28

CPC分类号： H01L21/7681 ,  H01L21/76804

摘要： A dual damascene process forms a two level metal interconnect structure by first providing a interlayer oxide over a device structure and covering the interlevel oxide layer with an etch stop layer. The etch stop layer is patterned to form openings corresponding to the pattern of the interconnects that are to be formed in the first level of the two level interconnect structure. After the etch stop layer is patterned, an intermetal oxide layer is provided over the etch stop layer. Because the etch stop layer is relatively thin, the topography formed on the surface of the intermetal oxide layer is relatively small. A photoresist mask is then provided over the intermetal oxide layer with openings in the mask exposing portions of the intermetal oxide layer in the pattern of the wiring lines to be provided in the second level of the interconnect structure. The intermetal oxide layer is etched and the etching process continues to form openings in the interlayer oxide where the interlayer oxide is exposed by the openings in the etch stop layer. Thus, in a single etching step, the openings for both the second level wiring lines and the first level interconnects are defined. Metal is then deposited over the structure and excess metal is removed by chemical mechanical polishing to define the two level interconnect structure.

摘要翻译： 双镶嵌工艺通过首先在器件结构上提供层间氧化物并用蚀刻停止层覆盖层间氧化物层，形成两层金属互连结构。 蚀刻停止层被图案化以形成对应于将要形成在两层互连结构的第一层中的互连图案的开口。 在蚀刻停止层被图案化之后，在蚀刻停止层上方提供金属间氧化物层。 因为蚀刻停止层相对较薄，所以形成在金属间氧化物层的表面上的形貌相对较小。 然后在金属间氧化物层之上提供光致抗蚀剂掩模，其中掩模中的开口在布线的图案中的金属间氧化物层的暴露部分中设置有互连结构的第二层。 蚀刻金属间氧化物层，并且蚀刻工艺继续在层间氧化物中形成开口，其中层间氧化物被蚀刻停止层中的开口暴露。 因此，在单个蚀刻步骤中，限定了用于二级布线和第一级互连的开口。 然后将金属沉积在结构上，通过化学机械抛光除去多余的金属以限定两层互连结构。