公开(公告)号：US4738895A

公开(公告)日：1988-04-19

申请号：US008333

申请日：1987-01-29

Applicant: Minoru Takada ,  Hidetaka Oohori ,  Takayoshi Nakajima

Inventor： Minoru Takada ,  Hidetaka Oohori ,  Takayoshi Nakajima

IPC: B27N3/04 ,  C08L97/02 ,  D04H1/04 ,  D04H1/26 ,  D04H1/4374 ,  D04H1/541 ,  D04H1/58 ,  B32B5/14

CPC classification number: B27N3/04 ,  C08L97/02 ,  Y10T428/253 ,  Y10T428/2929 ,  Y10T428/2931 ,  Y10T442/608 ,  Y10T442/638 ,  Y10T442/64 ,  Y10T442/641

Abstract: An improved woody fiber mat composed mainly of woody fibers, long fibers, thermoplastic fibers and a thermoset resin and moldable under heat and pressure into a product having a definite shape and very suitable to deep draw forming is provided, which mat is characterized in that the thermoplastic fibers are composite fibers composed of a plurality of components having different melting points; the fibers constituting the mat are entangled with each other and also subjected to melt adhesion and joining by a lower melting point component of the composite fibers; and the thermoset resin is in an uncured state.

Abstract translation: 本发明提供一种木质纤维毡，其主要由木质纤维，长纤维，热塑性纤维和热固性树脂组成，并且在加热和加压下成型为具有确定形状并非常适合深拉成形的产品，其特征在于： 热塑性纤维是由具有不同熔点的多种成分组成的复合纤维; 构成垫子的纤维彼此缠结并且还通过复合纤维的较低熔点成分进行熔融粘合和接合; 并且热固性树脂处于未固化状态。

公开(公告)号：US4356411A

公开(公告)日：1982-10-26

申请号：US101103

申请日：1979-12-07

Applicant: Yasoji Suzuki ,  Minoru Takada

Inventor： Yasoji Suzuki ,  Minoru Takada

IPC: H03K3/3562 ,  H03K3/289

CPC classification number: H03K3/3562

Abstract: Disclosed is a flip-flop circuit capable of high speed and of low power consumption which has a master flip-flop including a logic gate circuit, and a slave flip-flop circuit also including a logic gate circuit, and a means for supplying a preset signal or a clear signal to the logic gate circuit of the slave flip-flop circuit or to an output logic circuit. Specifically, a binary type flip-flop circuit with preset/clear functions suitable for a ring counter and a ripple counter, and assembled by means of integrated circuit technology, is disclosed.

Abstract translation: 公开了一种具有高速度和低功耗的触发器电路，其具有包括逻辑门电路的主触发器和还包括逻辑门电路的从触发器电路，以及用于提供预设 信号或清除信号发送到从触发器电路的逻辑门电路或输出逻辑电路。 具体地说，公开了一种具有适用于环形计数器和纹波计数器的预置/清除功能并通过集成电路技术组装的二进制触发器电路。

公开(公告)号：US4318117A

公开(公告)日：1982-03-02

申请号：US93201

申请日：1979-11-13

Applicant: Yasoji Suzuki ,  Minoru Takada ,  Yasushi Satoh ,  Hiroshi Osanai

Inventor： Yasoji Suzuki ,  Minoru Takada ,  Yasushi Satoh ,  Hiroshi Osanai

IPC: H01L29/08 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L27/092

Abstract: A MOS integrated circuit including P-channel MOS transistors, particularly for C-MOS inverter, in which the P-channel MOS transistor (12) has P.sup.+ drain (34), P.sup.+ source (36) connected to a +VDD circuit (42) via P.sup.+ and N.sup.+ diffusion layers (36.sub.1, 36.sub.2) and isolation gate (38). The P.sup.+ layer is partly replaced by, i.e. parallel- and/or serial-connected to the N.sup.+ layer so that an effective source diffusion resistance (R.sub.S) or the conductive resistance (R.sub.0) is lowered.

Abstract translation: 一种包括P沟道MOS晶体管的MOS集成电路，特别是用于C-MOS反相器的P沟道MOS晶体管，其中P沟道MOS晶体管（12）具有连接到+ VDD电路（42）的P +漏极（34），P +源极（36） 通过P +和N +扩散层（361,362）和隔离栅极（38）。 P +层被部分地替换为N +层的并联和/或串联连接，使得有效的源极扩散电阻（RS）或导电电阻（R0）降低。