摘要:
An architecture for an electronic controller operated using fuzzy logic, including an input section with a plurality of inputs for analog or digital signals, a central control unit provided with memories wherein fuzzy logic membership functions are stored, and a defuzzyfier section has its input section composed of a plurality of fuzzyfiers arranged in parallel and independent of one another, each fuzzyfier including an analog input and a digital input for receiving signals from external sensors, and digital outputs connected to the input of a corresponding read-only memory of the central unit to select the address of a memory word.
摘要:
A filter acting on digital image signals for apparatus of the video type includes at least first and second processing units adapted to elect an image edge, each processing unit includes an inferential circuit operating on fuzzy logic, which has first and second input terminals and an output terminal, and first and second comparison elements each having first and second input terminals and an output terminal, the input terminals being intended for receiving discrete digital signals of an image. The output terminals of the first and second comparison elements in the first processing unit are respectively connected to the first and second input terminals of the inferential circuit included in the first processing unit, and the output terminals of the first and second comparison elements in the second processing unit are respectively connected to the first and second input terminals of the inferential circuit included in the second processing unit.
摘要:
A television signal scanning conversion device of the type comprising at least one filtering block having a plurality of digital inputs which receive through an interface components of an interlaced television signal comprises also at lease one calculation block connected to the signal inputs and operating with fuzzy logic. The calculation block is capable of executing a switch between at least two different interpolation procedures, to wit interfield and intrafield.
摘要:
The digital filter includes a plurality of parallel adders, each whereof has a first input, a second input and an output; the parallel output of each adder is connected to the first input of the successive adder across a respective delay element. The second input of each adder is connected in parallel to the output of one of a plurality of memory banks, each whereof comprises a plurality of addressable memory cells, the addressing inputs whereof can be driven by a sampled digital signal to be filtered, and the memory cells of each bank contain a digital value which is equal to the product of a preset coefficient by the address of the cell itself.