公开(公告)号：US20080054980A1

公开(公告)日：2008-03-06

申请号：US11468815

申请日：2006-08-31

申请人： Maciej Bajkowski ,  George P. Hoekstra ,  Hamed Ghassemi

发明人： Maciej Bajkowski ,  George P. Hoekstra ,  Hamed Ghassemi

IPC分类号： H03L5/00

CPC分类号： H03K19/01855 ,  H03K3/356121

摘要： A level shifting circuit having a signal input that operates in a first voltage domain and a signal output that operates in a second voltage domain. In some embodiments, the level shifting circuit includes a clocked level shifter. In some embodiments, the level shifting circuit includes a level shifting latch that latches a translated output signal. In one example, the level shifting latch includes a latch portion and a stack of transistors with a transistor having a control electrode coupled to a clock input.

摘要翻译： 电平移动电路，其具有在第一电压域中操作的信号输入和在第二电压域中操作的信号输出。 在一些实施例中，电平移位电路包括时钟电平移位器。 在一些实施例中，电平移位电路包括锁存转换的输出信号的电平移位锁存器。 在一个示例中，电平移位锁存器包括具有耦合到时钟输入的控制电极的晶体管的锁存部分和晶体管堆叠。

公开(公告)号：US07443223B2

公开(公告)日：2008-10-28

申请号：US11468815

申请日：2006-08-31

申请人： Maciej Bajkowski ,  George P. Hoekstra ,  Hamed Ghassemi

发明人： Maciej Bajkowski ,  George P. Hoekstra ,  Hamed Ghassemi

IPC分类号： H03K19/0175

CPC分类号： H03K19/01855 ,  H03K3/356121

摘要： A level shifting circuit having a signal input that operates in a first voltage domain and a signal output that operates in a second voltage domain. In some embodiments, the level shifting circuit includes a clocked level shifter. In some embodiments, the level shifting circuit includes a level shifting latch that latches a translated output signal. In one example, the level shifting latch includes a latch portion and a stack of transistors with a transistor having a control electrode coupled to a clock input.

摘要翻译： 电平移动电路，其具有在第一电压域中操作的信号输入和在第二电压域中操作的信号输出。 在一些实施例中，电平移位电路包括时钟电平移位器。 在一些实施例中，电平移位电路包括锁存转换的输出信号的电平移位锁存器。 在一个示例中，电平移位锁存器包括具有耦合到时钟输入的控制电极的晶体管的锁存部分和晶体管堆叠。

公开(公告)号：US4866676A

公开(公告)日：1989-09-12

申请号：US172514

申请日：1988-03-24

申请人： Richard D. Crisp ,  George P. Hoekstra ,  George G. Watkins

发明人： Richard D. Crisp ,  George P. Hoekstra ,  George G. Watkins

IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24 ,  G11C29/36

CPC分类号： G11C29/78 ,  G11C29/24 ,  G11C29/36

摘要： A read/write memory has bit line pairs variously having a first or a second true/complement orientation. Data is selectively coupled to and from the bit line pairs to and from a data line pair via a column decoder. The memory has redundant bit line pairs aligned in the first true/complement arrangement. When a redundant bit line pair is implemented, the logic state of the data is inverted both for reading and for writing if the replaced bit line pair is of the second true/complement orientation. This results in the voltage impressed onto the memory cell for a given logic state is the same for the redundant bit line pair as for the bit line pair that it replaced.