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公开(公告)号：US4866676A
公开(公告)日：1989-09-12
申请号：US172514
申请日：1988-03-24
IPC分类号： G11C11/413 , G11C11/401 , G11C29/00 , G11C29/04 , G11C29/24 , G11C29/36
摘要： A read/write memory has bit line pairs variously having a first or a second true/complement orientation. Data is selectively coupled to and from the bit line pairs to and from a data line pair via a column decoder. The memory has redundant bit line pairs aligned in the first true/complement arrangement. When a redundant bit line pair is implemented, the logic state of the data is inverted both for reading and for writing if the replaced bit line pair is of the second true/complement orientation. This results in the voltage impressed onto the memory cell for a given logic state is the same for the redundant bit line pair as for the bit line pair that it replaced.
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公开(公告)号：US20140269131A1
公开(公告)日：2014-09-18
申请号：US13826427
申请日：2013-03-14
IPC分类号： G11C7/08
摘要： A memory device includes a plurality of sense amplifiers, an array of memory cells including a first subset of memory cells, and a plurality of word lines. Each word line is coupled to each memory cell in a respective row of the memory cells and each row of the memory cells includes one memory cell of the first subset of memory cells. Each of a plurality of control word lines is coupled to a respective one of the memory cells in the first subset of memory cells and each of the memory cells in the first subset of memory cells generates a sense amplifier control signal coupled to control operation of a respective one of the plurality of sense amplifiers.
摘要翻译： 存储器件包括多个读出放大器，包括存储器单元的第一子集的存储器单元阵列和多个字线。 每个字线被耦合到存储器单元的相应行中的每个存储器单元，并且每行存储器单元包括存储器单元的第一子集的一个存储单元。 多个控制字线中的每一个耦合到存储器单元的第一子集中的相应的一个存储器单元，并且存储器单元的第一子集中的每个存储单元产生一个读出放大器控制信号， 相应的多个读出放大器之一。
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公开(公告)号：US07564738B2
公开(公告)日：2009-07-21
申请号：US11464129
申请日：2006-08-11
IPC分类号： G11C8/16
CPC分类号： G11C8/10 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C8/18
摘要： A double-rate memory has an array of single word line memory cells arranged in rows and columns. The single word line memory cells provide and store data via a first port. Addressing and control circuitry is coupled to the array of single word line memory cells. The addressing and control circuitry receives an address enable signal to initiate an access of the array whereby an address is received, decoded, and corresponding data retrieved or stored. Edge detection circuitry receives a memory clock and provides the address enable signal upon each rising edge and each falling edge of the memory clock to perform two memory operations in a single cycle of the memory clock. A memory operation includes addressing the memory and storing data in the memory or retrieving and latching data from the memory. In another form a double-rate dual port memory permits two independent read/write memory accesses in a single memory cycle.
摘要翻译： 双速率存储器具有以行和列排列的单个字线存储单元阵列。 单个字线存储单元通过第一端口提供和存储数据。 寻址和控制电路耦合到单个字线存储单元的阵列。 寻址和控制电路接收地址使能信号以启动阵列的访问，由此接收，解码地址并检索或存储对应的数据。 边缘检测电路接收存储器时钟，并在存储器时钟的每个上升沿和每个下降沿提供地址使能信号，以在存储器时钟的单个周期中执行两个存储器操作。 存储器操作包括寻址存储器并将数据存储在存储器中或从存储器检索和锁存数据。 在另一种形式中，双速率双端口存储器允许在单个存储器周期中进行两个独立的读/写存储器存取。
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公开(公告)号：US06608789B2
公开(公告)日：2003-08-19
申请号：US10027547
申请日：2001-12-21
IPC分类号： G11C700
CPC分类号： G11C7/065
摘要： A sense amplifier (40) uses a body shorting device (60) to selectively electrically short circuit the bodies of two transistors (44, 48) that function as a differential sensing pair. Equalization of charge injected into the bodies functions to minimize offset voltage between the two bodies. The body shorting device selectively shorts the bodies in response to a body control signal after a sense operation and after asserting a precharging signal to initiate precharging of the sense amplifier's outputs.
摘要翻译： 读出放大器（40）使用主体短路装置（60）来选择性地使作为差分感测对的两个晶体管（44,48）的主体电短路。 注入到体内的电荷的均衡起到使两个物体之间的失调电压最小化的作用。 身体短路装置在感测操作之后并且在确定预充电信号以启动感测放大器的输出的预充电之后，响应于身体控制信号选择性地短路身体。
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公开(公告)号：US4802129A
公开(公告)日：1989-01-31
申请号：US128559
申请日：1987-12-03
IPC分类号： G11C7/10 , G11C7/22 , G11C11/419 , G11C7/00 , G11C8/00
CPC分类号： G11C11/419 , G11C7/10 , G11C7/22
摘要： A memory is written via data lines which are driven by a write driver. The data lines are coupled to a selected bit line pair as determined by a column address. The data lines are driven to a logic state representative of a data input signal by a write driver. The write driver is enabled during the presence of a write enable pulse. The write enable pulse is generated in response to a read mode to write mode transition and also in response to a transition of the data input signal. The data lines are precharged in response to a transition of the data input signal that occurs during the write mode.
摘要翻译： 通过由写入驱动器驱动的数据线写入存储器。 数据线被耦合到由列地址确定的所选位线对。 数据线由写入驱动器驱动到代表数据输入信号的逻辑状态。 在存在写使能脉冲时，写驱动器被使能。 写使能脉冲响应于写模式转换的读模式并且还响应于数据输入信号的转换而被产生。 响应于在写入模式期间发生的数据输入信号的转变，数据线被预充电。
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公开(公告)号：US20130290753A1
公开(公告)日：2013-10-31
申请号：US13689331
申请日：2012-11-29
申请人： Ravindraraj Ramaraju , Jianan Yang , Mark W. Jetton , Thomas W. Liston , George P. Hoekstra , Andrew C. Russell
发明人： Ravindraraj Ramaraju , Jianan Yang , Mark W. Jetton , Thomas W. Liston , George P. Hoekstra , Andrew C. Russell
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F1/3296 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： In accordance with at least one embodiment, column level power control granularity is provided to control a low power state of a memory using a drowsy column control bit to control the low power state at an individual column level to protect the memory from weak bit failure. In accordance with at least one embodiment, a method of using a dedicated row of bit cells in a memory array is provided wherein each bit in the row controls the low power state of a respective column in the array. A special control signal is used to access the word line, and the word line is outside of the regular word line address space. A mechanism is provided to designate the weak bit column and set the control bit corresponding to that particular column to disable the drowsy/low power state for that column.
摘要翻译： 根据至少一个实施例，提供列级功率控制粒度以使用昏迷列控制位来控制存储器的低功率状态，以控制单个列级的低功率状态，以保护存储器免于弱位故障。 根据至少一个实施例，提供了在存储器阵列中使用专用行位单元的方法，其中行中的每个位控制阵列中相应列的低功率状态。 使用特殊的控制信号来访问字线，字线在常规字线地址空间之外。 提供了一种机制来指定弱位列，并设置与该特定列相对应的控制位以禁用该列的困倦/低功率状态。
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公开(公告)号：US20100208537A1
公开(公告)日：2010-08-19
申请号：US12388922
申请日：2009-02-19
CPC分类号： G11C11/406 , G11C11/401 , G11C11/40622 , G11C29/02 , G11C29/023 , G11C29/50 , G11C29/50016 , G11C2029/0407 , G11C2211/4061
摘要： A method for refreshing a Dynamic Random Access Memory (DRAM) includes performing a refresh on at least a portion of the DRAM at a first refresh rate, and performing a refresh on a second portion of the DRAM at a second refresh rate. The second portion includes one or more rows of the DRAM which do not meet a data retention criteria at the first refresh rate, and the second refresh rate is greater than the first refresh rate.
摘要翻译： 一种用于刷新动态随机存取存储器（DRAM）的方法包括以第一刷新率在DRAM的至少一部分上执行刷新，并以第二刷新率在DRAM的第二部分上执行刷新。 第二部分包括在第一刷新率下不满足数据保留标准的一行或多行DRAM，并且第二刷新率大于第一刷新率。
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公开(公告)号：US20100107037A1
公开(公告)日：2010-04-29
申请号：US12260727
申请日：2008-10-29
CPC分类号： G06F11/1064
摘要： A method is provided for error correction of a memory. The method includes: providing a first memory and a second memory; initiating a read operation of the first memory to retrieve data; performing an error correction code (ECC) processing on the data, wherein the ECC processing for determining that at least a portion of the data is erroneous and for providing corrected data; and determining if an address of the erroneous data is stored in the second memory, if the address of the erroneous data is stored in the second memory, storing the corrected data in the second memory, and if the address of the erroneous data is not stored in the second memory, storing the address in the second memory.
摘要翻译： 提供了一种用于存储器的纠错的方法。 该方法包括：提供第一存储器和第二存储器; 启动第一存储器的读取操作以检索数据; 对所述数据执行纠错码（ECC）处理，其中所述ECC处理用于确定所述数据的至少一部分是错误的并且用于提供校正数据; 并且确定所述错误数据的地址是否存储在所述第二存储器中，如果所述错误数据的地址被存储在所述第二存储器中，则将所述校正数据存储在所述第二存储器中，并且所述错误数据的地址未被存储 在第二存储器中，将地址存储在第二存储器中。
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公开(公告)号：US07164293B2
公开(公告)日：2007-01-16
申请号：US10902204
申请日：2004-07-29
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A circuit (50) that receives dynamic signals performs both logic and latching to achieve high speed operation. The circuit has a clock that defines both an evaluation phase and a precharge phase in which the dynamic signals are evaluated during the evaluation phase. The circuit (50) functions by precharging a latch node (INT) during the evaluation phase then performing evaluation as well during the evaluation phase. The evaluation results in providing a valid logic state to the latch node. A latch circuit (54) latches this valid state during the precharge phase and holds it in this valid state during the precharge phase. This can be adapted to select which one of the dynamic signals is to be coupled and latched on the latch node (INT).
摘要翻译： 接收动态信号的电路（50）执行逻辑和锁存以实现高速操作。 电路具有定义评估阶段和预充电阶段的时钟，其中动态信号在评估阶段被评估。 电路（50）通过在评估阶段期间对锁存节点（INT）进行预充电来起作用，然后在评估阶段期间执行评估。 评估导致向锁存节点提供有效的逻辑状态。 锁存电路（54）在预充电阶段期间锁存该有效状态，并且在预充电阶段将其保持在该有效状态。 这可以适于选择哪个动态信号被耦合并锁存在锁存节点（INT）上。
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公开(公告)号：US5367494A
公开(公告)日：1994-11-22
申请号：US113632
申请日：1993-08-31
CPC分类号： G11C8/12 , G11C11/005 , G11C7/1042
摘要： A memory device (28) executes memory access operations of two or more storage locations concurrently. The memory device (28) is comprised of a plurality of memory bank decode logic circuits (30, 32, 56) and a plurality of memory banks (34, 52). Each of the decode logic circuits decodes a first information and control signal set to enable a first memory bank to begin and complete a memory access operation. Each memory bank is comprised of a plurality of latch circuits (39,40, 42, 50) to store a predetermined information and control signal set necessary to perform the memory access operation. A second control signal and information set may, therefore, enable a second memory bank within the memory device (28) to perform a second memory access operation concurrently in time with the first memory access operation.
摘要翻译： 存储器装置（28）同时执行两个或多个存储位置的存储器存取操作。 存储器件（28）由多个存储体解码逻辑电路（30,32,56）和多个存储器组（34,52）组成。 每个解码逻辑电路解码设置的第一信息和控制信号，以使第一存储体开始并完成存储器访问操作。 每个存储体由多个锁存电路（39,40,42,50）组成，以存储执行存储器访问操作所必需的预定信息和控制信号。 因此，第二控制信号和信息集可以使存储器装置（28）内的第二存储器组能够在第一存储器存取操作的同时执行第二存储器存取操作。
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