公开(公告)号：US06820106B1

公开(公告)日：2004-11-16

申请号：US09604620

申请日：2000-06-27

Applicant: Narsing K. Vijayrao ,  Chi Keung Lee ,  Sudarshan Kumar

Inventor： Narsing K. Vijayrao ,  Chi Keung Lee ,  Sudarshan Kumar

IPC: G06F738

CPC classification number: G06F7/5443 ,  G06F7/483 ,  G06F7/49936 ,  G06F7/49957 ,  G06F7/74

Abstract: A method and apparatus to increase the performance of a floating point multiplier accumulator (FMAC). The method comprises receiving three floating point numbers and computing a product of the first floating point number and the second floating point number and adding a third floating point number to produce a sum value and a carry value. A propagate value, a kill value and a generate value are then computed based on the sum value and the carry value. Simultaneously the sum value is added to the carry value to create a first result, the sum value is added to the carry value and incremented by one to create a second result, the sum value is added to the carry value and incremented by two to create a third result, and a decimal point position is determined. One of the first result, the second result and the third result is then selected responsive to a rounding mode and the decimal point position. The selected result is normalized based on the decimal point position. The apparatus comprises a multiplier with a propagate, kill, generate generator (PKG generator) coupled to it. An adder, a plus-oner, a plus-two-er and a leading zero anticipator (LZA) are each coupled to the PKG generator in parallel. A rounding control unit is coupled to the LZA and coupled to a multiplexor that outputs a result from one of the adder, the plus-oner, and the plus-two-er responsive to the rounding control unit. A normalization shifter is coupled to the multiplexor and the LZA.

Abstract translation: 一种提高浮点乘法器累加器（FMAC）性能的方法和装置。 该方法包括接收三个浮点数并计算第一个浮点数和第二个浮点数的乘积，并加上第三个浮点数以产生一个和值和一个进位值。 然后根据和值和进位值计算传播值，杀死值和生成值。 同时将总和值加到进位值以创建第一个结果，将和值添加到进位值并递增1以创建第二个结果，将总和值添加到进位值并递增2以创建 确定第三结果和小数点位置。 然后根据舍入模式和小数点位置选择第一个结果之一，第二个结果和第三个结果。 所选结果根据小数点位置进行归一化。 该装置包括具有耦合到其的传播，杀死，生成发生器（PKG发生器）的乘法器。 加法器，加法器，加二和前导零预测器（LZA）均并联耦合到PKG发生器。 四舍五入控制单元耦合到LZA，并且耦合到多路复用器，该多路复用器响应于舍入控制单元输出加法器，加上器和加二乘法器中的一个的结果。 归一化移位器耦合到多路复用器和LZA。

公开(公告)号：US06629194B2

公开(公告)日：2003-09-30

申请号：US09872965

申请日：2001-05-31

Applicant: Sudarshan Kumar ,  Gaurav G. Mehta ,  Sadhana Madhyastha ,  Jiann-Cherng Lan

Inventor： Sudarshan Kumar ,  Gaurav G. Mehta ,  Sadhana Madhyastha ,  Jiann-Cherng Lan

IPC: G06F1200

CPC classification number: G06F9/30141 ,  G06F9/3012 ,  G11C7/12 ,  G11C2207/007 ,  G11C2207/2281

Abstract: A memory includes a plurality of banks of memory elements. For a memory read access operation, bank enable logic coupled to each of the plurality of banks is responsive to an address of a memory element to be read to selectively deactivate a first precharge clock signal to be received by a first one of the banks that includes the memory element to be read. The bank enable logic is further responsive to the address to selectively maintain in an active state a second precharge clock signal to be received by a second one of the banks that does not include the memory element to be read.

公开(公告)号：US5661675A

公开(公告)日：1997-08-26

申请号：US414908

申请日：1995-03-31

Applicant: Kai J. Chin ,  Sudarshan Kumar

Inventor： Kai J. Chin ,  Sudarshan Kumar

IPC: G06F7/50 ,  G06F7/508 ,  H03K19/096 ,  H03K17/80

CPC classification number: G06F7/508 ,  H03K19/0963 ,  G06F2207/3872

Abstract: A logic circuit is described. The logic circuit generates a first signal state in response to a first set of input signals, generates a second signal state in response to a second set of input signals, activates a bypass switch in response to the first signal state, and bypasses a domino logic unit in response to the first signal state.

Abstract translation: 描述逻辑电路。 逻辑电路响应于第一组输入信号产生第一信号状态，响应于第二组输入信号产生第二信号状态，响应于第一信号状态激活旁路开关，并绕过多米诺逻辑 响应于第一信号状态的单元。

公开(公告)号：US5136539A

公开(公告)日：1992-08-04

申请号：US285202

申请日：1988-12-16

Applicant: Sudarshan Kumar

Inventor： Sudarshan Kumar

IPC: G06F7/50 ,  G06F7/506 ,  G06F7/507 ,  G06F7/508

CPC classification number: G06F7/506 ,  G06F7/508

Abstract: An metal-oxide-semiconductor (MOS) partitioned carry lookahead adder fabricated from a plurality of four bit slice blocks. Each block provides four sum signals and provides a block carry signal. The blocks are organized into groups of optimum size with logic in each group to generate a group propagate signals. Each block has a block carry line with a single transistor connected between the input and output terminals of the block. The blocks employ an intermediate carry circuit for computing sums in place of full adders. In addition, there is a main carry line with transistors controlled by the group propagate signals. For a 32 bit adder, the maximum pass gate delay in the carry chain is three pass gates.

Abstract translation: 由多个四位片块制造的金属氧化物半导体（MOS）分区进位前瞻加法器。 每个块提供四个和信号并提供块进位信号。 块被组织成最佳尺寸的组，每组中具有逻辑以产生组传播信号。 每个块具有块载入线，其中单个晶体管连接在块的输入和输出端子之间。 块使用中间携带电路来计算总和代替全加器。 此外，还有一个主输送线，晶体管由组传播信号控制。 对于32位加法器，进位链中的最大通过门延迟是三通门。