公开(公告)号：US20120042127A1

公开(公告)日：2012-02-16

申请号：US12871108

申请日：2010-08-30

Applicant: Greggory D. Donley ,  William Alexander Hughes ,  Narsing K. Vijayrao

Inventor： Greggory D. Donley ,  William Alexander Hughes ,  Narsing K. Vijayrao

IPC: G06F12/08

CPC classification number: G06F12/0895

Abstract: A method and apparatus for partitioning a cache includes determining an allocation of a subcache out of a plurality of subcaches within the cache for association with a compute unit out of a plurality of compute units. Data is processed by the compute unit, and the compute unit evicts a line. The evicted line is written to the subcache associated with the compute unit.

Abstract translation: 用于分割高速缓存的方法和装置包括确定高速缓存内的多个子程序中的子程序的分配，以便与多个计算单元中的计算单元相关联。 数据由计算单元处理，并且计算单元排除一行。 被驱逐的行被写入与计算单元相关联的子程序。

公开(公告)号：US08606999B2

公开(公告)日：2013-12-10

申请号：US12871108

申请日：2010-08-30

Applicant: Greggory D. Donley ,  William Alexander Hughes ,  Narsing K. Vijayrao

Inventor： Greggory D. Donley ,  William Alexander Hughes ,  Narsing K. Vijayrao

IPC: G06F12/00

CPC classification number: G06F12/0895

Abstract: A method and apparatus for partitioning a cache includes determining an allocation of a subcache out of a plurality of subcaches within the cache for association with a compute unit out of a plurality of compute units. Data is processed by the compute unit, and the compute unit evicts a line. The evicted line is written to the subcache associated with the compute unit.

Abstract translation: 用于分割高速缓存的方法和装置包括确定高速缓存内的多个子程序中的子程序的分配，以便与多个计算单元中的计算单元相关联。 数据由计算单元处理，并且计算单元排除一行。 被驱逐的行被写入与计算单元相关联的子程序。

公开(公告)号：US06820106B1

公开(公告)日：2004-11-16

申请号：US09604620

申请日：2000-06-27

Applicant: Narsing K. Vijayrao ,  Chi Keung Lee ,  Sudarshan Kumar

Inventor： Narsing K. Vijayrao ,  Chi Keung Lee ,  Sudarshan Kumar

IPC: G06F738

CPC classification number: G06F7/5443 ,  G06F7/483 ,  G06F7/49936 ,  G06F7/49957 ,  G06F7/74

Abstract: A method and apparatus to increase the performance of a floating point multiplier accumulator (FMAC). The method comprises receiving three floating point numbers and computing a product of the first floating point number and the second floating point number and adding a third floating point number to produce a sum value and a carry value. A propagate value, a kill value and a generate value are then computed based on the sum value and the carry value. Simultaneously the sum value is added to the carry value to create a first result, the sum value is added to the carry value and incremented by one to create a second result, the sum value is added to the carry value and incremented by two to create a third result, and a decimal point position is determined. One of the first result, the second result and the third result is then selected responsive to a rounding mode and the decimal point position. The selected result is normalized based on the decimal point position. The apparatus comprises a multiplier with a propagate, kill, generate generator (PKG generator) coupled to it. An adder, a plus-oner, a plus-two-er and a leading zero anticipator (LZA) are each coupled to the PKG generator in parallel. A rounding control unit is coupled to the LZA and coupled to a multiplexor that outputs a result from one of the adder, the plus-oner, and the plus-two-er responsive to the rounding control unit. A normalization shifter is coupled to the multiplexor and the LZA.

Abstract translation: 一种提高浮点乘法器累加器（FMAC）性能的方法和装置。 该方法包括接收三个浮点数并计算第一个浮点数和第二个浮点数的乘积，并加上第三个浮点数以产生一个和值和一个进位值。 然后根据和值和进位值计算传播值，杀死值和生成值。 同时将总和值加到进位值以创建第一个结果，将和值添加到进位值并递增1以创建第二个结果，将总和值添加到进位值并递增2以创建 确定第三结果和小数点位置。 然后根据舍入模式和小数点位置选择第一个结果之一，第二个结果和第三个结果。 所选结果根据小数点位置进行归一化。 该装置包括具有耦合到其的传播，杀死，生成发生器（PKG发生器）的乘法器。 加法器，加法器，加二和前导零预测器（LZA）均并联耦合到PKG发生器。 四舍五入控制单元耦合到LZA，并且耦合到多路复用器，该多路复用器响应于舍入控制单元输出加法器，加上器和加二乘法器中的一个的结果。 归一化移位器耦合到多路复用器和LZA。

公开(公告)号：US6111435A

公开(公告)日：2000-08-29

申请号：US343961

申请日：1999-06-30

Applicant: Jiann-Cherng James Lan ,  Mahadevamurty Nemani ,  Narsing K. Vijayrao ,  Wenjie Jiang ,  Sudarshan Kumar

Inventor： Jiann-Cherng James Lan ,  Mahadevamurty Nemani ,  Narsing K. Vijayrao ,  Wenjie Jiang ,  Sudarshan Kumar

IPC: H03K17/693 ,  H03K19/173 ,  H03K19/20

CPC classification number: H03K17/693 ,  H03K19/1731

Abstract: A circuit includes first and second pull-up transistors having first and second drains, respectively, each coupled to separate voltage clamps. The gates of each of the two pull-up transistors are coupled to a clock signal line. The circuit further includes a shared pull-down transistor, the gate of which is coupled to the clock signal line. The drain of the shared pull-down transistor is coupled to the first drain via at least one pull-down transistor in series with the shared pull-down transistor. The drain of the shared pull-down transistor is also coupled to the second drain via at least one pull-down transistor in series with the shared pull-down transistor. This circuit may be found useful in multiplexing applications.

Abstract translation: 电路包括第一和第二上拉晶体管，其分别具有分别耦合到单独的电压钳位的第一和第二漏极。 两个上拉晶体管中的每一个的栅极耦合到时钟信号线。 电路还包括共享下拉晶体管，其栅极耦合到时钟信号线。 共享下拉晶体管的漏极经由与共用下拉晶体管串联的至少一个下拉晶体管耦合到第一漏极。 共享下拉晶体管的漏极还通过与共享下拉晶体管串联的至少一个下拉晶体管耦合到第二漏极。 该电路可用于多路复用应用。

公开(公告)号：US6058403A

公开(公告)日：2000-05-02

申请号：US130379

申请日：1998-08-06

Applicant: Narsing K. Vijayrao ,  Sudarshan Kumar

Inventor： Narsing K. Vijayrao ,  Sudarshan Kumar

IPC: H03K19/096 ,  G06F7/74 ,  G06F7/00

CPC classification number: G06F7/74

Abstract: A broken stack domino priority encoder to provide a set of voltages to uniquely identify the position of a leading one or leading zero in a binary word, the domino priority encoder comprising a by-pass stack of nMOSFETs and a broken stack of nMOSFETs to discharge various nodes. The stack depth of nMOSFETs between each node and ground is minimized in order to maximize switching speed of the priority encoder.

Abstract translation: 一种破碎的堆叠多米诺骨牌优先编码器，用于提供一组电压以唯一地识别二进制字中的前导或前导零的位置，多米诺骨牌优先级编码器包括nMOSFET的旁路堆叠和破坏的nMOSFET堆叠，以排放各种 节点。 为了最大化优先编码器的切换速度，使每个节点和地之间的nMOSFET的堆叠深度最小化。