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公开(公告)号：US06628539B2
公开(公告)日：2003-09-30
申请号：US09872975
申请日：2001-05-31
IPC分类号： G11C1900
CPC分类号： G11C11/419 , G06F9/30036 , G06F9/30105 , G06F9/3012 , G06F9/30141
摘要： A multi-entry register file cell includes multiple memory elements. A value stored in each of the multiple memory elements may be individually read from the register file cell in response to asserting a single word line.
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公开(公告)号：US5880608A
公开(公告)日：1999-03-09
申请号：US774261
申请日：1996-12-27
申请人： Gaurav G. Mehta , David Harris , S. Deo Singh
发明人： Gaurav G. Mehta , David Harris , S. Deo Singh
IPC分类号： H03K19/096 , H03K19/00
CPC分类号： H03K19/096
摘要： The present invention is a novel method of interfacing static logic to domino logic. A static logic block is connected to one input of a domino evaluation tree. The domino evaluation tree operates only during a brief window of time, while an evaluation control block is ON. Since the input to the domino gate only must be stable during this brief window of time, there is no need to latch the output of the static logic.
摘要翻译： 本发明是将静态逻辑与多米诺骨牌逻辑进行接口的新颖方法。 静态逻辑块连接到多米诺骨牌评估树的一个输入。 多米诺骨牌评估树仅在短时间内运行，而评估控制块为ON。 由于输入多米诺骨牌门只能在这个简短的时间窗口内稳定下来，所以不需要锁定静态逻辑的输出。
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3.发明授权
公开(公告)号：US5821775A
公开(公告)日：1998-10-13
申请号：US774262
申请日：1996-12-27
申请人： Gaurav G. Mehta , David Harris , S. Deo Singh
发明人： Gaurav G. Mehta , David Harris , S. Deo Singh
IPC分类号： H03K19/0185 , H03K19/096
CPC分类号： H03K19/0963 , H03K19/01855
摘要： The present invention is an improved interface between monotonic and non-monotonic domino logic. A monotonic domino logic block is clocked by CLK. The last stage of the monotonic domino logic is clocked by the delayed clock, DCLK, to extend its evaluation period beyond Phase I by a brief window of time, t.sub.d. The true output and the inverted output of the last stage of the monotonic domino logic block are inputs to a non-monotonic domino evaluation tree. The non-monotonic domino evaluation tree operates while an evaluation control block is ON. The evaluation control block is ON only during that extension of the evaluation period, t.sub.d, for a time less than or equal to the period t.sub.d. Since the output of the last stage of the monotonic logic block remains stable during this extended evaluation period, and the non-monotonic domino evaluation tree operates at most during this window of time, there is no need to use latches or use a dual rail implementation for the monotonic logic.
摘要翻译： 本发明是单调和非单调多米诺骨牌之间的改进的接口。 单调的多米诺骨牌逻辑块由CLK计时。 单调多米诺骨牌逻辑的最后阶段由延迟时钟DCLK计时，通过简短的时间td将其评估期延长到第一阶段。 单调多米诺骨牌逻辑块的最后一级的真实输出和反相输出是非单调多米诺骨牌评估树的输入。 非单调多米诺骨牌评估树在评估控制块为ON时运行。 评价控制块在评估期间td的延长期间为ON，时间小于或等于期间td。 由于单调逻辑块的最后阶段的输出在该扩展的评估期间保持稳定，并且非单调多米诺骨牌评估树在该时间窗口中最多运行，因此不需要使用锁存器或使用双轨实现 对于单调逻辑。
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4.发明授权Method and apparatus for reducing power consumption in a domino logic by reducing unnecessary toggles 失效通过减少不必要的切换来降低多米诺骨牌中的功耗的方法和装置
公开(公告)号：US6005417A
公开(公告)日：1999-12-21
申请号：US885120
申请日：1997-06-30
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A method and apparatus for reducing power consumption in a domino logic is provided. An input of the domino logic block has as an output of an upstream logic block. A first state, e.g. default or idle, of the output of the upstream logic block is determined. The an output of the domino logic block corresponding to the said first state is determined. A logic block is modified, such that the output of the domino logic block for the first state is the same as a precharge state of the output. This results in preventing the output of the domino logic block from toggling when the first state is the input to the domino logic block.
摘要翻译： 提供了一种用于降低多米诺骨牌逻辑中的功耗的方法和装置。 多米诺骨牌逻辑块的输入具有上游逻辑块的输出。 第一状态，例如 确定上游逻辑块的输出的默认或空闲状态。 确定与所述第一状态相对应的多米诺骨牌逻辑块的输出。 修改逻辑块，使得用于第一状态的多米诺骨牌逻辑块的输出与输出的预充电状态相同。 这导致当第一状态是多米诺骨牌逻辑块的输入时，防止多米诺骨牌逻辑块的输出切换。
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公开(公告)号：US06341099B1
公开(公告)日：2002-01-22
申请号：US09672950
申请日：2000-09-29
IPC分类号： G11C700
CPC分类号： G11C7/1087 , G11C7/1006 , G11C7/1078
摘要： A technique for reducing power consumption in a data storage device consisting of a number of data cells includes arranging the number of data cells in clusters, each cluster having more than one data cell having their data enable inputs connected together. A data write bus is provided to provide data enable signals to the data enable inputs of the number of data cells. A number of pass gates are respectively disposed between the clusters and the write data bus. The pass gates are selectively enabled to allow data enable signals to pass from the write data bus to the data enable inputs of the more than one data cell of a selected one or more of the clusters. A number of inverters may be respectively disposed between the number of pass gates and the clusters. A number of sustainer circuits may be respectively connected to the number of pass gates. Each of the pass gates may include a pair of field effect transistors which may be complementary field effect transistors. Each of the sustainer circuits may include a pair of back-to-back inverters.
摘要翻译： 一种用于降低由多个数据单元组成的数据存储设备中的功耗的技术包括将数据单元的数量排列成簇，每个簇具有多个数据单元，其数据使能输入连接在一起。 提供数据写总线以向数据单元数量的数据使能输入提供数据使能信号。 在簇和写入数据总线之间分别设置多个通过门。 通过门有选择地使允许数据使能信号从写入数据总线传递到所选择的一个或多个集群的多个数据单元的数据使能输入。 多个反相器可以分别设置在通过门数和簇之间。 多个保持器电路可以分别连接到通孔的数量。 每个通过栅极可以包括一对场效应晶体管，其可以是互补场效应晶体管。 每个维持器电路可以包括一对背对背反相器。
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公开(公告)号：US06629194B2
公开(公告)日：2003-09-30
申请号：US09872965
申请日：2001-05-31
IPC分类号： G06F1200
CPC分类号： G06F9/30141 , G06F9/3012 , G11C7/12 , G11C2207/007 , G11C2207/2281
摘要： A memory includes a plurality of banks of memory elements. For a memory read access operation, bank enable logic coupled to each of the plurality of banks is responsive to an address of a memory element to be read to selectively deactivate a first precharge clock signal to be received by a first one of the banks that includes the memory element to be read. The bank enable logic is further responsive to the address to selectively maintain in an active state a second precharge clock signal to be received by a second one of the banks that does not include the memory element to be read.
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