公开(公告)号：US20130289965A1

公开(公告)日：2013-10-31

申请号：US13457722

申请日：2012-04-27

申请人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Keunwoo Kim

发明人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Keunwoo Kim

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/10

摘要： A method for analyzing circuits includes identifying one or more device zones in a full device structure. The device zones provide areas of interest to be analyzed. A partial device is generated that representatively includes the one or more device zones. Analytical meshes of the partial device are reduced by employing physical characteristics of the full device structure. The partial device is simulated, using a processor, to obtain device output information in the areas of interest that is representative of the full device structure. Systems are also disclosed.

公开(公告)号：US20130289948A1

公开(公告)日：2013-10-31

申请号：US13611359

申请日：2012-09-12

申请人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Keunwoo Kim

发明人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Keunwoo Kim

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/10

摘要： A method for analyzing circuits includes identifying one or more device zones in a full device structure. The device zones provide areas of interest to be analyzed. A partial device is generated that representatively includes the one or more device zones. Analytical meshes of the partial device are reduced by employing physical characteristics of the full device structure. The partial device is simulated, using a processor, to obtain device output information in the areas of interest that is representative of the full device structure. Systems are also disclosed.

摘要翻译： 一种用于分析电路的方法包括识别完整设备结构中的一个或多个设备区域。 设备区域提供要分析的感兴趣区域。 生成代表性地包括一个或多个设备区域的部分设备。 通过采用整个装置结构的物理特性来减少部分装置的分析网格。 使用处理器来模拟部分设备，以获得代表整个设备结构的感兴趣区域中的设备输出信息。 还披露了系统。

公开(公告)号：US08606557B2

公开(公告)日：2013-12-10

申请号：US12698759

申请日：2010-02-02

申请人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Keunwoo Kim

发明人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Keunwoo Kim

IPC分类号： G06F17/50 ,  G06G7/62

CPC分类号： G06F17/50

摘要： Techniques for electronic circuit design simulation are provided. In one aspect, a method for electronic circuit design simulation includes the following steps. A model (e.g., a physics-based model) of the circuit design is created. Error tables are created containing data related to one or more regions of the circuit design. The model is modified with data from the error tables. The modified model is used to simulate the circuit design.

摘要翻译： 提供电子电路设计仿真技术。 一方面，电子电路设计仿真的方法包括以下步骤。 创建电路设计的模型（例如，基于物理的模型）。 创建包含与电路设计的一个或多个区域有关的数据的错误表。 该模型使用错误表中的数据进行修改。 修改后的模型用于模拟电路设计。

公开(公告)号：US08548788B2

公开(公告)日：2013-10-01

申请号：US13609542

申请日：2012-09-11

申请人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Keunwoo Kim

发明人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Keunwoo Kim

IPC分类号： G06F17/50

CPC分类号： G06F17/5018 ,  G06F2217/10

摘要： A single finite element mesh is generated for predicting performance of an integrated circuit design. A plurality of sample points are identified for conducting a variability study on at least one parameter associated with the integrated circuit design. The sample points are selected to predict performance of the integrated circuit design when subject to variations in the at least one parameter due to variations in manufacturing processes to be used to manufacture the integrated circuit design. A parameterized netlist is generated corresponding to each of the sample points. A technology computer aided design (TCAD) simulation is run for each of the parameterized netlists, using the single finite element mesh for each of the parameterized netlists, until convergence is achieved, to obtain, for each of the parameterized netlists, at least one metric indicative of the performance of the integrated circuit design. A predicted design yield is developed for the integrated circuit design.

摘要翻译： 生成单个有限元网格以预测集成电路设计的性能。 识别多个采样点用于对与集成电路设计相关联的至少一个参数进行变异性研究。 选择采样点以预测由于要用于制造集成电路设计的制造工艺的变化而受到至少一个参数的变化时的集成电路设计的性能。 生成对应于每个采样点的参数化网表。 对每个参数化网表执行技术计算机辅助设计（TCAD）模拟，使用每个参数化网表的单个有限元网格，直到达到收敛，为每个参数化网表获得至少一个度量 指示集成电路设计的性能。 为集成电路设计开发了预测的设计产量。

公开(公告)号：US20130060551A1

公开(公告)日：2013-03-07

申请号：US13609542

申请日：2012-09-11

申请人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Keunwoo Kim

发明人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Keunwoo Kim

IPC分类号： G06F17/50

CPC分类号： G06F17/5018 ,  G06F2217/10

摘要： A single finite element mesh is generated for predicting performance of an integrated circuit design. A plurality of sample points are identified for conducting a variability study on at least one parameter associated with the integrated circuit design. The sample points are selected to predict performance of the integrated circuit design when subject to variations in the at least one parameter due to variations in manufacturing processes to be used to manufacture the integrated circuit design. A parameterized netlist is generated corresponding to each of the sample points. A technology computer aided design (TCAD) simulation is run for each of the parameterized netlists, using the single finite element mesh for each of the parameterized netlists, until convergence is achieved, to obtain, for each of the parameterized netlists, at least one metric indicative of the performance of the integrated circuit design. A predicted design yield is developed for the integrated circuit design.

摘要翻译： 生成单个有限元网格以预测集成电路设计的性能。 识别多个采样点用于对与集成电路设计相关联的至少一个参数进行变异性研究。 选择采样点以预测由于要用于制造集成电路设计的制造工艺的变化而受到至少一个参数的变化时的集成电路设计的性能。 生成对应于每个采样点的参数化网表。 对每个参数化网表执行技术计算机辅助设计（TCAD）模拟，使用每个参数化网表的单个有限元网格，直到达到收敛，为每个参数化网表获得至少一个度量 指示集成电路设计的性能。 为集成电路设计开发了预测的设计产量。

公开(公告)号：US20110191091A1

公开(公告)日：2011-08-04

申请号：US12698759

申请日：2010-02-02

申请人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Keunwoo Kim

发明人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Keunwoo Kim

IPC分类号： G06F17/50

CPC分类号： G06F17/50

摘要： Techniques for electronic circuit design simulation are provided. In one aspect, a method for electronic circuit design simulation includes the following steps. A model (e.g., a physics-based model) of the circuit design is created. Error tables are created containing data related to one or more regions of the circuit design. The model is modified with data from the error tables. The modified model is used to simulate the circuit design.

摘要翻译： 提供电子电路设计仿真技术。 一方面，电子电路设计仿真的方法包括以下步骤。 创建电路设计的模型（例如，基于物理的模型）。 创建包含与电路设计的一个或多个区域有关的数据的错误表。 该模型使用错误表中的数据进行修改。 修改后的模型用于模拟电路设计。

公开(公告)号：US08515724B2

公开(公告)日：2013-08-20

申请号：US12820741

申请日：2010-06-22

申请人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Keunwoo Kim

发明人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Keunwoo Kim

IPC分类号： G06F17/50

CPC分类号： G06F17/5018 ,  G06F2217/10

摘要： A single finite element mesh is generated for predicting performance of an integrated circuit design. A plurality of sample points are identified for conducting a variability study on at least one parameter associated with the integrated circuit design. The sample points are selected to predict performance of the integrated circuit design when subject to variations in the at least one parameter due to variations in manufacturing processes to be used to manufacture the integrated circuit design. A parameterized netlist is generated corresponding to each of the sample points. A technology computer aided design (TCAD, e.g., finite element) simulation is run for each of the parameterized netlists, using the single finite element mesh for each of the parameterized netlists, until convergence is achieved, to obtain, for each of the parameterized netlists, at least one metric indicative of the performance of the integrated circuit design. A predicted design yield is developed for the integrated circuit design, based on the at least one metric determined for each of the parameterized netlists. In at least some instances, an importance sampling technique is tightly integrated with the TCAD process.

摘要翻译： 生成单个有限元网格以预测集成电路设计的性能。 识别多个采样点用于对与集成电路设计相关联的至少一个参数进行变异性研究。 选择采样点以预测由于要用于制造集成电路设计的制造工艺的变化而受到至少一个参数的变化时的集成电路设计的性能。 生成对应于每个采样点的参数化网表。 对于每个参数化的网表，运行技术计算机辅助设计（TCAD，例如有限元）模拟，使用每个参数化网表的单个有限元网格，直到达到收敛，为每个参数化网表 ，指示集成电路设计的性能的至少一个度量。 基于为每个参数化网表确定的至少一个度量，针对集成电路设计开发了预测的设计收益。 在至少一些情况下，重要性采样技术与TCAD过程紧密集成。

公开(公告)号：US08472271B2

公开(公告)日：2013-06-25

申请号：US13030341

申请日：2011-02-18

申请人： James W. Dawson ,  Rajiv V. Joshi ,  Noam Jungmann ,  Elazar Kachir ,  Rouwaida N. Kanj ,  Ehud Nir ,  Donald W. Plass

发明人： James W. Dawson ,  Rajiv V. Joshi ,  Noam Jungmann ,  Elazar Kachir ,  Rouwaida N. Kanj ,  Ehud Nir ,  Donald W. Plass

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C7/1048 ,  G11C11/413

摘要： Systems and methods for determining optimal memory device precharge voltages are provided herein. In addition, systems and methods for providing localized sense amplification and circuit assist circuitry are described herein. Embodiments provide for determining precharge multipliers that may be used to determine the optimal precharge voltage based on a precharge source voltage. According to embodiments, the precharge source voltage may be Vdd or Vcs. Optimizing the precharge voltage maximizes memory device performance and functional characteristics, including, but not limited to, stability, efficiency, power, writability, and reliability.

摘要翻译： 本文提供了用于确定最佳存储器件预充电电压的系统和方法。 此外，本文描述了用于提供局部感测放大和电路辅助电路的系统和方法。 实施例提供了用于确定预充电乘法器，其可以用于基于预充电源电压来确定最佳预充电电压。 根据实施例，预充电源电压可以是Vdd或Vcs。 优化预充电电压使存储器件性能和功能特性最大化，包括但不限于稳定性，效率，功率，写入性和可靠性。

公开(公告)号：US20120213023A1

公开(公告)日：2012-08-23

申请号：US13030341

申请日：2011-02-18

申请人： James W. Dawson ,  Rajiv V. Joshi ,  Noam Jungmann ,  Elazar Kachir ,  Rouwaida N. Kanj ,  Ehud Nir ,  Donald W. Plass

发明人： James W. Dawson ,  Rajiv V. Joshi ,  Noam Jungmann ,  Elazar Kachir ,  Rouwaida N. Kanj ,  Ehud Nir ,  Donald W. Plass

IPC分类号： G11C7/12

CPC分类号： G11C7/12 ,  G11C7/1048 ,  G11C11/413

摘要： Systems and methods for determining optimal memory device precharge voltages are provided herein. In addition, systems and methods for providing localized sense amplification and circuit assist circuitry are described herein. Embodiments provide for determining precharge multipliers that may be used to determine the optimal precharge voltage based on a precharge source voltage. According to embodiments, the precharge source voltage may be Vdd or Vcs. Optimizing the precharge voltage maximizes memory device performance and functional characteristics, including, but not limited to, stability, efficiency, power, writability, and reliability.

摘要翻译： 本文提供了确定最佳存储器件预充电电压的系统和方法。 此外，本文描述了用于提供局部感测放大和电路辅助电路的系统和方法。 实施例提供了用于确定预充电乘法器，其可以用于基于预充电源电压来确定最佳预充电电压。 根据实施例，预充电源电压可以是Vdd或Vcs。 优化预充电电压使存储器件性能和功能特性最大化，包括但不限于稳定性，效率，功率，写入性和可靠性。

公开(公告)号：US09411921B2

公开(公告)日：2016-08-09

申请号：US13457722

申请日：2012-04-27

申请人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Keunwoo Kim

发明人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Keunwoo Kim

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/10

摘要： A method for analyzing circuits includes identifying one or more device zones in a full device structure. The device zones provide areas of interest to be analyzed. A partial device is generated that representatively includes the one or more device zones. Analytical meshes of the partial device are reduced by employing physical characteristics of the full device structure. The partial device is simulated, using a processor, to obtain device output information in the areas of interest that is representative of the full device structure. Systems are also disclosed.

摘要翻译： 一种用于分析电路的方法包括识别完整设备结构中的一个或多个设备区域。 设备区域提供要分析的感兴趣区域。 生成代表性地包括一个或多个设备区域的部分设备。 通过采用整个装置结构的物理特性来减少部分装置的分析网格。 使用处理器来模拟部分设备，以获得代表整个设备结构的感兴趣区域中的设备输出信息。 还披露了系统。