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    Serial link receiver with improved bandwidth and accurate eye monitor
    31.
    发明授权
    Serial link receiver with improved bandwidth and accurate eye monitor 有权

    公开(公告)号：US10601615B2

    公开(公告)日：2020-03-24

    申请号：US16161547

    申请日：2018-10-16

    Applicant: Rambus Inc.

    Inventor： Marko Aleksic ,  Pravin Kumar Venkatesan ,  Simon Li ,  Nikhil Vaidya

    IPC: H04L25/03 ,  H03M13/21 ,  H03M13/00 ,  H04L1/00

    Abstract: A receiver includes a decision circuit, a circuit to adjust an input signal of the decision circuit, a correction circuit and a control circuit. The decision circuit makes a data decision based on an input signal of the decision circuit. The circuit to adjust the input signal of the decision circuit adjusts the input signal of the decision circuit based on an input correction signal. The correction circuit combines a plurality of signals corresponding to different input correction parameters into a preliminary input correction signal. An input of the correction circuit is coupled to an output of the decision circuit. The control circuit maps the preliminary input correction signal into the input correction signal using a nonlinear code mapping.

    Serial link receiver with improved bandwidth and accurate eye monitor
    33.
    发明授权
    Serial link receiver with improved bandwidth and accurate eye monitor 有权

    公开(公告)号：US10135642B2

    公开(公告)日：2018-11-20

    申请号：US15438571

    申请日：2017-02-21

    Applicant: Rambus Inc.

    Inventor： Marko Aleksić ,  Pravin Kumar Venkatesan ,  Simon Li ,  Nikhil Vaidya

    IPC: H03H7/30 ,  H04L25/03 ,  H03M13/21 ,  H03M13/00 ,  H04L1/00

    Abstract: A receiver includes a decision circuit, a circuit to adjust an input signal of the decision circuit, a correction circuit and a control circuit. The decision circuit makes a data decision based on an input signal of the decision circuit. The circuit to adjust the input signal of the decision circuit adjusts the input signal of the decision circuit based on an input correction signal. The correction circuit combines a plurality of signals corresponding to different input correction parameters into a preliminary input correction signal. An input of the correction circuit is coupled to an output of the decision circuit. The control circuit maps the preliminary input correction signal into the input correction signal using a nonlinear code mapping.

    Supporting calibration for sub-rate operation in clocked memory systems
    35.
    发明授权
    Supporting calibration for sub-rate operation in clocked memory systems 有权
    支持定时存储器系统中子速率操作的校准

    公开(公告)号：US09349422B2

    公开(公告)日：2016-05-24

    申请号：US14687739

    申请日：2015-04-15

    Applicant: Rambus Inc.

    Inventor： Akash Bansal ,  Yohan U. Frans ,  Kishore V. Kasamsetty ,  Todd Bystrom ,  Simon Li ,  Arun Vaidyanath

    IPC: G11C7/22 ,  G11C29/02 ,  G06F1/10

    CPC classification number: G11C7/22 ,  G06F1/10 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

    Abstract: The disclosed embodiments related to a clocked memory system which performs a calibration operation at a full-rate frequency to determine a full-rate calibration state that specifies a delay between a clock signal and a corresponding data signal in the clocked memory system. Next, the clocked memory system uses the full-rate calibration state to calculate a sub-rate calibration state, which is associated with a sub-rate frequency (e.g., ½, ¼ or ⅛ of the full-rate frequency). The system then uses this sub-rate calibration state when the clocked memory system is operating at the sub-rate frequency. This calculation of the sub-rate state calibration states eliminates the need to perform an additional time-consuming calibration operation for each sub-rate.

    Abstract translation: 所公开的实施例涉及一种时钟存储器系统，其以全速率频率执行校准操作，以确定指定时钟信号与时钟控制的存储器系统中的相应数据信号之间的延迟的全速率校准状态。 接下来，时钟存储器系统使用全速率校准状态来计算与子速率频率（例如，全速率频率的1/2，¼或⅛）相关联的子速率校准状态。 当时钟存储器系统以子速率频率工作时，系统然后使用该子速率校准状态。 子速率状态校准状态的这种计算消除了对每个子速率执行附加耗时的校准操作的需要。

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