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公开(公告)号：US20100153683A1
公开(公告)日：2010-06-17
申请号：US12336342
申请日：2008-12-16
申请人： Ravi K. Arimilli , Balaram Sinharoy
发明人： Ravi K. Arimilli , Balaram Sinharoy
CPC分类号： G06F9/345
摘要： A processor includes at least one execution unit that executes instructions, at least one register file, coupled to the at least one execution unit, that buffers operands for access by the at least one execution unit, and an instruction sequencing unit that fetches instructions for execution by the execution unit. The processor further includes an operand data structure and an address generation accelerator. The operand data structure specifies a first relationship between addresses of sequential accesses within a first address region and a second relationship between addresses of sequential accesses within a second address region. The address generation accelerator computes a first address of a first memory access in the first address region by reference to the first relationship and a second address of a second memory access in the second address region by reference to the second relationship.
摘要翻译： 处理器包括执行指令的至少一个执行单元，耦合到所述至少一个执行单元的至少一个寄存器文件，其缓冲由所述至少一个执行单元访问的操作数，以及指令排序单元，其提取用于执行的指令 由执行单位。 处理器还包括操作数数据结构和地址生成加速器。 操作数数据结构指定第一地址区域内的顺序访问的地址与第二地址区域内的顺序存取的地址之间的第一关系。 参考第二关系，地址生成加速器通过参考第一关系和第二地址区中的第二存储器访问的第二地址来计算第一地址区中的第一存储器访问的第一地址。
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公开(公告)号：US20090198975A1
公开(公告)日：2009-08-06
申请号：US12024546
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Ronald N. Kalla , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Ronald N. Kalla , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F9/315
CPC分类号： G06F9/30043 , G06F9/30032 , G06F9/3834 , G06F9/3885
摘要： A data processing system has a processor, a memory, and an instruction set architecture (ISA) that includes: (1) an asynchronous memory mover (AMM) store (ST) instruction initiates an asynchronous memory move operation that moves data from a first memory location having a first real address to a second memory location having a second real address by: (a) first performing a move of the data in virtual address space utilizing a source effective address a destination effective address; and (b) when the move is completed, completing a physical move of the data to the second memory location, independent of the processor. The ISA further provides (2) an AMM terminate ST instruction for stopping an ongoing AMM operation before completion of the AMM operation, and (3) a LD CMP instruction for checking a status of an AMM operation.
摘要翻译： 数据处理系统具有处理器，存储器和指令集架构（ISA），其包括：（1）异步存储器移动器（AMM）存储器（ST）指令发起异步存储器移动操作，其将数据从第一存储器 具有通过以下方式具有第二实际地址的具有第一实际地址的位置：（a）首先使用源有效地址执行虚拟地址空间中的数据移动目的地有效地址; 和（b）当移动完成时，完成数据到第二存储器位置的物理移动，而与处理器无关。 ISA进一步提供（2）在完成AMM操作之前停止正在进行的AMM操作的AMM终止ST指令，以及（3）用于检查AMM操作状态的LD CMP指令。
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33.发明申请LAUNCHING MULTIPLE CONCURRENT MEMORY MOVES VIA A FULLY ASYNCHRONOOUS MEMORY MOVER 失效启动多个同时存储器通过充分的异步存储器移动公开(公告)号：US20090198939A1
公开(公告)日：2009-08-06
申请号：US12024690
申请日：2008-02-01
IPC分类号： G06F12/02
CPC分类号： G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3836 , G06F9/3851 , G06F12/10
摘要： A data processing system has an asynchronous memory mover, which includes multiple sets of registers for storing addressing and control parameters utilized to generate one or more asynchronous memory move (AMM) operations. The memory mover detects a receipt of a first set of parameters in a first set of registers from the processor. The processor forwards the parameters after the processor initiates a data move in virtual address space, utilizing a source effective address and a destination effective address. The memory mover responds to receiving the first set of parameters by generating and launching a first asynchronous memory move (AMM) operation. When the memory mover receives a second set of parameters in a second set of registers before the first AMM operation completes, the memory mover generates and launches a second AMM operation concurrently with the first AMM operation if no address conflicts exist.
摘要翻译： 数据处理系统具有异步存储器移动器，其包括用于存储用于生成一个或多个异步存储器移动（AMM）操作的寻址和控制参数的多组寄存器。 存储器移动器检测来自处理器的第一组寄存器中的第一组参数的接收。 处理器在虚拟地址空间中启动数据移动后，使用源有效地址和目标有效地址，处理器转发参数。 存储器移动器响应于通过生成和启动第一异步存储器移动（AMM）操作来接收第一组参数。 当存储器移动器在第一个AMM操作完成之前在第二组寄存器中接收到第二组参数时，如果不存在地址冲突，则存储器移动器生成并与第一个AMM操作同时启动第二个AMM操作。
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公开(公告)号：US08356151B2
公开(公告)日：2013-01-15
申请号：US12024504
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Ronald N. Kalla , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Ronald N. Kalla , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F12/02
CPC分类号： G06F9/30043 , G06F12/0831 , G06F12/0862 , G06F12/1027
摘要： A method performed in a data processing system initiates an asynchronous memory move (AMM) operation, whereby a processor performs a move of data in virtual address space from a first effective address to a second effective address and forwards parameters of the AMM operation to asynchronous memory mover logic for completion of the physical movement of data from a first memory location to a second memory location. The processor executes a second operation, which checks a status of the completion of the data move and returns a notification indicating the status. The notification indicates a status, which includes one of: data move in progress; data move totally done; data move partially done; data move cannot be performed; and occurrence of a translation look-aside buffer invalidate entry (TLBIE) operation. The processor initiates one or more actions in response to the notification received.
摘要翻译： 在数据处理系统中执行的方法启动异步存储器移动（AMM）操作，由此处理器执行将虚拟地址空间中的数据从第一有效地址移动到第二有效地址，并将AMM操作的参数转发到异步存储器 用于完成数据从第一存储器位置到第二存储器位置的物理移动的移动器逻辑。 处理器执行第二操作，其检查数据移动完成的状态，并返回指示状态的通知。 该通知表示状态，其中包括：数据移动进行中的一个; 数据移动完成; 数据移动部分完成; 无法执行数据移动; 以及出现翻译后备缓冲区无效条目（TLBIE）操作。 处理器响应于收到的通知发起一个或多个动作。
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35.发明授权Mechanisms for communicating with an asynchronous memory mover to perform AMM operations 有权与异步存储器移动器进行通信以执行AMM操作的机制公开(公告)号：US08245004B2
公开(公告)日：2012-08-14
申请号：US12024560
申请日：2008-02-01
IPC分类号： G06F12/00
CPC分类号： G06F9/30032 , G06F12/0831 , G06F12/0862 , G06F12/10
摘要： A data processing system includes a set of architected registers within which the processor places state and other information to communicate with the asynchronous memory mover in order to initiate and control an AMM operation. The asynchronous memory mover performs an asynchronous memory move (AMM) operation in response to receiving a set of parameters within the architected registers, which parameters are associated with an AMM store instruction executed by the processor to initiates a move of data in virtual space before placing the information in the architected registers. The architected registers are processor architected registers, defined on a per thread basis by a compiler, or memory mapped architected registers allocated for communicating with the asynchronous memory mover during a bind and subsequent execution of an application. The architected registers are also utilized to store state information to enable a restore to a point before execution of the AMM operation.
摘要翻译： 数据处理系统包括一组架构寄存器，处理器将处理器置于与异步存储器移动器通信的状态和其它信息，以启动和控制AMM操作。 异步存储器移动器响应于在结构化寄存器内接收到一组参数而执行异步存储器移动（AMM）操作，哪些参数与处理器执行的AMM存储指令相关联，以在放置之前启动虚拟空间中的数据移动 建筑登记册中的信息。 架构寄存器是由编译器在每个线程基础上定义的处理器架构寄存器，或者在应用程序的绑定和后续执行期间分配用于与异步存储器移动器进行通信的内存映射架构寄存器。 架构寄存器还用于存储状态信息，以便在执行AMM操作之前恢复到一个点。
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公开(公告)号：US08140801B2
公开(公告)日：2012-03-20
申请号：US12191655
申请日：2008-08-14
申请人： Ravi K. Arimilli , Rama K. Govindaraju , Peter H. Hochschild , Bruce G. Mealey , Satya P. Sharma , Balaram Sinharoy
发明人： Ravi K. Arimilli , Rama K. Govindaraju , Peter H. Hochschild , Bruce G. Mealey , Satya P. Sharma , Balaram Sinharoy
IPC分类号： G06F12/00
CPC分类号： G06F9/3834 , G06F9/3004 , G06F9/3824
摘要： A system, method, and computer program product for semi-synchronously copying data from a first portion of memory to a second portion of memory are disclosed. The method comprises receiving, in a processor, a call for a semi-synchronous memory copy operation. The semi-synchronous memory copy operation preserves temporal persistence of validity for a virtual source address corresponding to a source location in a memory and a virtual target address corresponding to a target location in the memory by setting a flag bit. The call includes at least the virtual source address, the virtual target address, and an indicator identifying a number of bytes to be copied. The memory copy operation is placed in a queue for execution by a memory controller. The queue is coupled to the memory controller. At least one subsequent instruction is continued to be executed as the subsequent instruction becomes available from an instruction pipeline.
摘要翻译： 公开了一种用于将数据从存储器的第一部分半数同步地复制到存储器的第二部分的系统，方法和计算机程序产品。 该方法包括在处理器中接收对半同步存储器复制操作的呼叫。 半同步存储器复制操作通过设置标志位来保持对应于存储器中的源位置的虚拟源地址和对应于存储器中的目标位置的虚拟目标地址的有效性的时间持续性。 该呼叫至少包括虚拟源地址，虚拟目标地址和标识要复制的字节数的指示符。 存储器复制操作被放置在队列中以由存储器控制器执行。 队列耦合到存储器控制器。 随着随后的指令从指令流水线可用，继续执行至少一个后续指令。
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37.发明授权Completion of asynchronous memory move in the presence of a barrier operation 失效在存在障碍操作的情况下完成异步存储器移动公开(公告)号：US07991981B2
公开(公告)日：2011-08-02
申请号：US12024513
申请日：2008-02-01
CPC分类号： G06F9/30087 , G06F9/30032 , G06F9/3004 , G06F9/3834 , G06F9/3885 , G06F12/0831 , G06F12/0862 , G06F12/10
摘要： A method within a data processing system by which a processor executes an asynchronous memory move (AMM) store (ST) instruction to complete a corresponding AMM operation in parallel with an ongoing (not yet completed), previously issued barrier operation. The processor receives the AMM ST instruction after executing the barrier operation (or SYNC instruction) and before the completion of the barrier operation or SYNC on the system fabric. The processor continues executing the AMM ST instruction, which performs a move in virtual address space and then triggers the generation of the AMM operation. The AMM operation proceeds while the barrier operation continues, independent of the processor. The processor stops further execution of all other memory access requests, excluding AMM ST instructions that are received after the barrier operation, but before completion of the barrier operation.
摘要翻译： 数据处理系统中的方法，通过该方法，处理器执行异步存储器移动（AMM）存储（ST）指令以与正在进行的（未完成）先前发布的屏障操作并行地完成对应的AMM操作。 执行屏障操作（或SYNC指令）后，在系统结构上完成屏障操作或SYNC之前，处理器接收AMM ST指令。 处理器继续执行AMM ST指令，其在虚拟地址空间中执行移动，然后触发AMM操作的生成。 无障碍操作继续进行，与处理器无关，AMM操作继续进行。 处理器停止所有其他存储器访问请求的进一步执行，排除在屏障操作之后但在屏障操作完成之前接收的AMM ST指令。
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38.发明授权公开(公告)号：US07930504B2
公开(公告)日：2011-04-19
申请号：US12024575
申请日：2008-02-01
CPC分类号： G06F12/10 , G06F9/30032 , G06F9/3834 , G06F9/3861 , G06F12/0815 , G06F12/1027 , G06F13/28
摘要： A method within a data processing system in which a processor handles conflicts, which occur during performance by an asynchronous memory mover of an asynchronous memory move (AMM) operation. The asynchronous memory mover performs an asynchronous memory move (AMM) operation by which the actual data is moved from a source to a destination memory location, independent of the processor. The memory mover sets a flag bit to indicate that the asynchronous memory mover is currently performing an AMM operation at the memory. When the processor receives a memory access operation, the processor checks the value of the flag bit before issuing the new memory access operation, and checks the associated address of the AMM operation to determine possible address conflicts. The processor then evaluates and responds to address conflicts to prevent corruption of data during an AMM operation.
摘要翻译： 数据处理系统中的方法，其中处理器处理由异步存储器移动（AMM）操作的异步存储器移动器执行期间发生的冲突。 异步存储器移动器执行异步存储器移动（AMM）操作，通过该操作将实际数据从源移动到目的地存储器位置，与处理器无关。 存储器移动器设置一个标志位，以指示异步存储器移动器当前在存储器上执行AMM操作。 当处理器接收到存储器访问操作时，处理器在发出新的存储器访问操作之前检查标志位的值，并且检查AMM操作的相关联的地址以确定可能的地址冲突。 然后，处理器评估并响应地址冲突，以防止在AMM操作期间数据损坏。
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39.发明申请Techniques for Cache Injection in a Processor System Responsive to a Specific Instruction Sequence 失效针对特定指令序列的处理器系统中缓存注入的技术公开(公告)号：US20100070717A1
公开(公告)日：2010-03-18
申请号：US12212961
申请日：2008-09-18
CPC分类号： G06F12/0862 , G06F12/0831 , G06F12/0897 , G06F2212/6024
摘要： A technique for performing cache injection includes monitoring an instruction stream for a specific instruction sequence. Addresses on a bus are then monitored, at a cache, in response to detecting the specific instruction sequence a determined number of times. Ownership of input/output data on the bus is then acquired by the cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block stored in the cache.
摘要翻译： 用于执行高速缓存注入的技术包括监视特定指令序列的指令流。 响应于检测到特定指令序列确定的次数，在总线上的地址被监视在高速缓存。 当总线上的地址（与输入/输出数据相关联）对应于存储在高速缓存中的数据块的地址时，总线上的输入/输出数据的所有权由高速缓存获取。
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公开(公告)号：US20090198950A1
公开(公告)日：2009-08-06
申请号：US12024239
申请日：2008-02-01
CPC分类号： G06F12/0862 , G06F2212/6028
摘要： A processor includes a first address translation engine, a second address translation engine, and a prefetch engine. The first address translation engine is configured to determine a first memory address of a pointer associated with a data prefetch instruction. The prefetch engine is coupled to the first translation engine and is configured to fetch content, included in a first data block (e.g., a first cache line) of a memory, at the first memory address. The second address translation engine is coupled to the prefetch engine and is configured to determine a second memory address based on the content of the memory at the first memory address. The prefetch engine is also configured to fetch (e.g., from the memory or another memory) a second data block (e.g., a second cache line) that includes data at the second memory address.
摘要翻译： 处理器包括第一地址转换引擎，第二地址转换引擎和预取引擎。 第一地址转换引擎被配置为确定与数据预取指令相关联的指针的第一存储器地址。 预取引擎被耦合到第一翻译引擎，并被配置为在第一存储器地址处提取包含在存储器的第一数据块（例如，第一高速缓存行）中的内容。 第二地址转换引擎耦合到预取引擎，并且被配置为基于第一存储器地址处的存储器的内容来确定第二存储器地址。 预取引擎还被配置为从第二存储器地址提取包括数据的第二数据块（例如，第二高速缓存行）（例如，从存储器或另一存储器）。
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