Abstract:
An efficient software download to a configurable communication device is disclosed herein. The method of efficiently downloading software begins with a step of receiving a request to configure a communication device to run a communication application. The communication device being configured has a plurality of function blocks with a fixed portion of hardware and a flexible portion of hardware, wherein the same plurality of function blocks is capable of operating a plurality of communication applications. In a next step, the capability of the fixed portion and the flexible portion of hardware of the communication device is evaluated for a capability of implementing the communication application. Next, configuration information only for the flexible portion of hardware of the communication device is transmitted to the communication device to enable it to operate the communication application. An identification of the communication application is also transmitted to the communication device for purposes of tracking its implementation.
Abstract:
A configurable all-digital coherent demodulator system for spread spectrum digital communications is disclosed herein. The demodulator system includes an extended and long code demodulator (ELCD) coupled to a traffic channel demodulator (TCD) and a parameter estimator (PE). The demodulator also includes a pilot assisted correction device (PACD) that is coupled to the PE and the TCD. The ELCD provides a code-demodulated signal to the TCD and the PE. In turn, the TCD provides a demodulated output data signal to the PE. The PACD corrects the phase error of the demodulated output data based on an error estimate that is fed forward from the PE. Accumulation operations in the ELCD, TCD, and PE are all programmable. Similarly, a phase delay in the PACD is also programmable to provide synchronization with the error estimate from the PE.
Abstract:
A wireless spread spectrum communication platform for processing a communication signal is disclosed herein. The wireless communication platform includes a first computing element, a second computing element, and a reconfigurable interconnect. The first computing element is coupled to the second computing element via the reconfigurable interconnect. A design configuration of the first computing element is heterogeneous with respect to a design configuration of the second computing element. The reconfigurable interconnect has an uncommitted architecture, thereby allowing it to be configured by an outside source to couple portions of the first reconfigurable interconnect with portions of the second reconfigurable interconnect in a variety of combinations. The first computing element, the second computing element, and the reconfigurable interconnect operable to perform discrete functions suitable for processing of the communication signal.
Abstract:
A configurable all-digital coherent demodulator system for spread spectrum digital communications is disclosed herein. The demodulator system includes an extended and long code demodulator (ELCD) coupled to a traffic channel demodulator (TCD) and a parameter estimator (PE). The demodulator also includes a pilot assisted correction device (PACD) that is coupled to the PE and the TCD. The ELCD provides a code-demodulated signal to the TCD and the PE. In turn, the TCD provides a demodulated output data signal to the PE. The PACD corrects the phase error of the demodulated output data based on an error estimate that is fed forward from the PE. Accumulation operations in the ELCD, TCD, and PE are all programmable. Similarly, a phase delay in the PACD is also programmable to provide synchronization with the error estimate from the PE.
Abstract:
An apparatus for digitally processing signals within wireless communications base-stations which includes a channel pooling signal processor and a digital signal processor. The channel pooling signal processor includes a plurality of computation units typically realized in a heterogeneous multiprocessing architecture, a test interface for testing the function of the plurality of the computation units, a general-purpose microprocessor for managing the dataflow into and out of the channel pooling signal processor as well as effecting the control and configuration of the computation units, and an interconnect mechanism for connecting the plurality of computation units to the input, output, test interface, and the general-purpose microprocessor.
Abstract:
A method of profiling disparate communications and signal processing standards. The method begins with selection of a set of communications and signal processing standards for analysis. Next, functions performed by the set of communications and signal processing standards are identified and ranked according to computational intensity. A set of high computational intensity functions are then selected for implementation as kernels, the set of kernels forming a programmable processor that enables implementation of any one of the set of communications and signal processing standards.
Abstract:
A digital wireless communication device comprises a software-programmable processor, a heterogeneous reconfigurable multiprocessing logic circuit, and a bus connecting the software-programmable processor and the heterogeneous reconfigurable multiprocessing logic circuit. The heterogeneous reconfigurable multiprocessing logic circuit comprises a set of heterogeneous signal processing kernels and a reconfigurable data router interconnecting the heterogeneous signal processing kernels. The software-programmable processor is selected from the group comprising: a digital signal processor and a central processing unit. The architecture provides the ability to reconfigure a single product platform for multiple standards, applications, services, and quality-of service, instead of developing multiple hardware platforms to establish the same collective functionality. The architecture also provides the ability to use software programming techniques to reduce product development time and achieve rapid and comprehensive product customization. The invention extends the performance efficiency of microprocessors and digital signal processors via the augmentation of data paths and control paths through a reconfigurable co-processing machine. The reconfigurability of the data path optimizes the performance of the data flow in the algorithms implemented on the processor.
Abstract:
A spread spectrum receiver for use in spread spectrum communication systems is disclosed. The spread spectrum receiver of the present invention includes an analog-to-digital converter for receiving an analog spread spectrum signal, and for converting the received analog signal to a digital signal. The spread spectrum receiver also includes a digital frequency offset correction device, for modifying the digital signal in accordance with a frequency correction term signal to thereby correct for frequency offset in the received analog signal. The spread spectrum receiver also contains a Rake receiver. The spread spectrum receiver searches through the modified digital signal to identify M of the main and multipath return signals having the strongest signal strengths. The identified main and multipath return signals are processed in accordance with predetermined maximum likelihood techniques to thereby generate phase correction and maximal-ratio combining weighting factors for each of the M signals, as well as the overall frequency correction term signal.