公开(公告)号：US06353921B1

公开(公告)日：2002-03-05

申请号：US09560438

申请日：2000-04-28

申请人： Edwin S. Law ,  Kiran B. Buch ,  Glenn A. Baxter ,  Raymond C. Pang

发明人： Edwin S. Law ,  Kiran B. Buch ,  Glenn A. Baxter ,  Raymond C. Pang

IPC分类号： G06F1750

CPC分类号： G06F17/5045

摘要： A hybrid HardWire device is provided that comprises a gate array core and a set of mask programmable I/O cells having I/O characteristics similar to those of an FPGA, i.e., sufficiently the same so the HardWire device can be used as a drop-in replacement for the FPGA with no redesign of the original system. Using this HardWire device, a user's design originally implemented in an FPGA can be emulated in the HardWire device, which then replaces the FPGA in the same board at a lower cost. In another embodiment, the I/O cells are mask programmable such that they can emulate the I/O characteristics of FPGAs from any of two or more FPGA families. This ability reduces the number of separate HardWire devices that must be designed, manufactured, tested, stored, and sold, and also simplifies the software required to convert designs to the new device. Some embodiments of the invention can also emulate other programmable devices such as PLDs.

摘要翻译： 提供了一种混合HardWire器件，其包括门阵列核心和一组具有类似于FPGA的I / O特性的掩码可编程I / O单元，即足够相同，因此HardWire器件可以用作下拉电阻， 替代FPGA而不重新设计原始系统。 使用这种HardWire设备，最初在FPGA中实现的用户设计可以在HardWire设备中进行仿真，然后以较低的成本替换同一块电路板中的FPGA。 在另一个实施例中，I / O单元是掩模可编程的，使得它们可以从两个或多个FPGA系列中的任何一个模拟FPGA的I / O特性。 这种能力减少了必须设计，制造，测试，存储和销售的单独的HardWire设备的数量，还简化了将设计转换为新设备所需的软件。 本发明的一些实施例还可以模拟其他可编程设备，例如PLD。

公开(公告)号：US6134517A

公开(公告)日：2000-10-17

申请号：US384714

申请日：1999-08-26

申请人： Glenn A. Baxter ,  Kiran B. Buch ,  Raymond C. Pang ,  Edwin S. Law

发明人： Glenn A. Baxter ,  Kiran B. Buch ,  Raymond C. Pang ,  Edwin S. Law

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318519

摘要： A method of implementing a boundary scan chain is provided using a programmable IC that includes dedicated boundary scan logic having a programmable boundary scan bit-order. Boundary scan cells are provided, each cell being capable of providing the boundary scan functions associated with one I/O pad. In a mask programmable device, dedicated tracks are provided for adding mask programmable interconnect lines. In other programmable ICs such as FPGAs or PLDs, programmable interconnect lines are provided. In either case, the interconnect lines are used to implement the boundary scan data chain. Using these lines, the programmed device can "swap the order" of I/O cells in the boundary scan data chain, or leave cells out of the chain entirely. In one embodiment, the interconnect lines traverse each cell, programmably connecting the data inputs and outputs of adjacent or non-adjacent boundary scan cells. In other embodiments, the interconnect lines are physically located outside the boundary scan cells, either in a ring between the cell and the core or in the core itself.

摘要翻译： 使用包括具有可编程边界扫描位顺序的专用边界扫描逻辑的可编程IC来提供实现边界扫描链的方法。 提供了边界扫描单元，每个单元能够提供与一个I / O垫相关联的边界扫描功能。 在掩模可编程设备中，提供专用轨道用于添加掩模可编程互连线。 在其他可编程IC（例如FPGA或PLD）中，提供可编程互连线。 在任一情况下，互连线用于实现边界扫描数据链。 使用这些线路，编程设备可以在边界扫描数据链中“交换I / O单元”的顺序，或将单元格完全从链中留出。 在一个实施例中，互连线穿过每个单元，可编程地连接相邻或非相邻边界扫描单元的数据输入和输出。 在其他实施例中，互连线物理地位于边界扫描单元外部，无论是在单元和芯之间的环中还是在芯本身中。

公开(公告)号：US6120551A

公开(公告)日：2000-09-19

申请号：US937809

申请日：1997-09-29

申请人： Edwin S. Law ,  Kiran B. Buch ,  Glenn A. Baxter ,  Raymond C. Pang

发明人： Edwin S. Law ,  Kiran B. Buch ,  Glenn A. Baxter ,  Raymond C. Pang

IPC分类号： G06F17/50 ,  G06F17/00

CPC分类号： G06F17/5045

摘要： A hybrid HardWire device is provided that comprises a gate array core and a set of mask programmable I/O cells having I/O characteristics similar to those of an FPGA, i.e., sufficiently the same so the HardWire device can be used as a drop-in replacement for the FPGA with no redesign of the original system. Using this HardWire device, a user's design originally implemented in an FPGA can be emulated in the HardWire device, which then replaces the FPGA in the same board at a lower cost. In another embodiment, the I/O cells are mask programmable such that they can emulate the I/O characteristics of FPGAs from any of two or more FPGA families. This ability reduces the number of separate HardWire devices that must be designed, manufactured, tested, stored, and sold, and also simplifies the software required to convert designs to the new device. Some embodiments of the invention can also emulate other programmable devices such as PLDs.

摘要翻译： 提供了一种混合HardWire器件，其包括门阵列核心和一组具有类似于FPGA的I / O特性的掩码可编程I / O单元，即足够相同，因此HardWire器件可以用作下拉电阻， 替代FPGA而不重新设计原始系统。 使用这种HardWire设备，最初在FPGA中实现的用户设计可以在HardWire设备中进行仿真，然后以较低的成本替换同一块电路板中的FPGA。 在另一个实施例中，I / O单元是掩模可编程的，使得它们可以从两个或多个FPGA系列中的任何一个模拟FPGA的I / O特性。 这种能力减少了必须设计，制造，测试，存储和销售的单独的HardWire设备的数量，还简化了将设计转换为新设备所需的软件。 本发明的一些实施例还可以模拟其他可编程设备，例如PLD。

公开(公告)号：US5991908A

公开(公告)日：1999-11-23

申请号：US939757

申请日：1997-09-29

申请人： Glenn A. Baxter ,  Kiran B. Buch ,  Raymond C. Pang ,  Edwin S. Law

发明人： Glenn A. Baxter ,  Kiran B. Buch ,  Raymond C. Pang ,  Edwin S. Law

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318519

摘要： A programmable IC is provided that includes dedicated boundary scan logic having a programmable boundary scan bit-order. Boundary scan cells are provided, each cell being capable of providing the boundary scan functions associated with one I/O pad. In a mask programmable device, dedicated tracks are provided for adding mask programmable interconnect lines. In other programmable ICs such as FPGAs or PLDs, programmable interconnect lines are provided. In either case, the interconnect lines are used to implement the boundary scan data chain. Using these lines, the programmed device can "swap the order" of I/O cells in the boundary scan data chain, or leave cells out of the chain entirely. In one embodiment, the interconnect lines traverse each cell, programmably connecting the data inputs and outputs of adjacent or non-adjacent boundary scan cells. In other embodiments, the interconnect lines are physically located outside the boundary scan cells, either in a ring between the cell and the core or in the core itself.

摘要翻译： 提供了一种可编程IC，其包括具有可编程边界扫描比特顺序的专用边界扫描逻辑。 提供了边界扫描单元，每个单元能够提供与一个I / O垫相关联的边界扫描功能。 在掩模可编程设备中，提供专用轨道用于添加掩模可编程互连线。 在其他可编程IC（例如FPGA或PLD）中，提供可编程互连线。 在任一情况下，互连线用于实现边界扫描数据链。 使用这些线路，编程设备可以在边界扫描数据链中“交换I / O单元”的顺序，或将单元格完全从链中留出。 在一个实施例中，互连线穿过每个单元，可编程地连接相邻或非相邻边界扫描单元的数据输入和输出。 在其他实施例中，互连线物理地位于边界扫描单元外部，无论是在单元和芯之间的环中还是在芯本身中。