公开(公告)号：US06353921B1

公开(公告)日：2002-03-05

申请号：US09560438

申请日：2000-04-28

申请人： Edwin S. Law ,  Kiran B. Buch ,  Glenn A. Baxter ,  Raymond C. Pang

发明人： Edwin S. Law ,  Kiran B. Buch ,  Glenn A. Baxter ,  Raymond C. Pang

IPC分类号： G06F1750

CPC分类号： G06F17/5045

摘要： A hybrid HardWire device is provided that comprises a gate array core and a set of mask programmable I/O cells having I/O characteristics similar to those of an FPGA, i.e., sufficiently the same so the HardWire device can be used as a drop-in replacement for the FPGA with no redesign of the original system. Using this HardWire device, a user's design originally implemented in an FPGA can be emulated in the HardWire device, which then replaces the FPGA in the same board at a lower cost. In another embodiment, the I/O cells are mask programmable such that they can emulate the I/O characteristics of FPGAs from any of two or more FPGA families. This ability reduces the number of separate HardWire devices that must be designed, manufactured, tested, stored, and sold, and also simplifies the software required to convert designs to the new device. Some embodiments of the invention can also emulate other programmable devices such as PLDs.

摘要翻译： 提供了一种混合HardWire器件，其包括门阵列核心和一组具有类似于FPGA的I / O特性的掩码可编程I / O单元，即足够相同，因此HardWire器件可以用作下拉电阻， 替代FPGA而不重新设计原始系统。 使用这种HardWire设备，最初在FPGA中实现的用户设计可以在HardWire设备中进行仿真，然后以较低的成本替换同一块电路板中的FPGA。 在另一个实施例中，I / O单元是掩模可编程的，使得它们可以从两个或多个FPGA系列中的任何一个模拟FPGA的I / O特性。 这种能力减少了必须设计，制造，测试，存储和销售的单独的HardWire设备的数量，还简化了将设计转换为新设备所需的软件。 本发明的一些实施例还可以模拟其他可编程设备，例如PLD。

公开(公告)号：US6134517A

公开(公告)日：2000-10-17

申请号：US384714

申请日：1999-08-26

申请人： Glenn A. Baxter ,  Kiran B. Buch ,  Raymond C. Pang ,  Edwin S. Law

发明人： Glenn A. Baxter ,  Kiran B. Buch ,  Raymond C. Pang ,  Edwin S. Law

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318519

摘要： A method of implementing a boundary scan chain is provided using a programmable IC that includes dedicated boundary scan logic having a programmable boundary scan bit-order. Boundary scan cells are provided, each cell being capable of providing the boundary scan functions associated with one I/O pad. In a mask programmable device, dedicated tracks are provided for adding mask programmable interconnect lines. In other programmable ICs such as FPGAs or PLDs, programmable interconnect lines are provided. In either case, the interconnect lines are used to implement the boundary scan data chain. Using these lines, the programmed device can "swap the order" of I/O cells in the boundary scan data chain, or leave cells out of the chain entirely. In one embodiment, the interconnect lines traverse each cell, programmably connecting the data inputs and outputs of adjacent or non-adjacent boundary scan cells. In other embodiments, the interconnect lines are physically located outside the boundary scan cells, either in a ring between the cell and the core or in the core itself.

摘要翻译： 使用包括具有可编程边界扫描位顺序的专用边界扫描逻辑的可编程IC来提供实现边界扫描链的方法。 提供了边界扫描单元，每个单元能够提供与一个I / O垫相关联的边界扫描功能。 在掩模可编程设备中，提供专用轨道用于添加掩模可编程互连线。 在其他可编程IC（例如FPGA或PLD）中，提供可编程互连线。 在任一情况下，互连线用于实现边界扫描数据链。 使用这些线路，编程设备可以在边界扫描数据链中“交换I / O单元”的顺序，或将单元格完全从链中留出。 在一个实施例中，互连线穿过每个单元，可编程地连接相邻或非相邻边界扫描单元的数据输入和输出。 在其他实施例中，互连线物理地位于边界扫描单元外部，无论是在单元和芯之间的环中还是在芯本身中。

公开(公告)号：US6120551A

公开(公告)日：2000-09-19

申请号：US937809

申请日：1997-09-29

申请人： Edwin S. Law ,  Kiran B. Buch ,  Glenn A. Baxter ,  Raymond C. Pang

发明人： Edwin S. Law ,  Kiran B. Buch ,  Glenn A. Baxter ,  Raymond C. Pang

IPC分类号： G06F17/50 ,  G06F17/00

CPC分类号： G06F17/5045

摘要： A hybrid HardWire device is provided that comprises a gate array core and a set of mask programmable I/O cells having I/O characteristics similar to those of an FPGA, i.e., sufficiently the same so the HardWire device can be used as a drop-in replacement for the FPGA with no redesign of the original system. Using this HardWire device, a user's design originally implemented in an FPGA can be emulated in the HardWire device, which then replaces the FPGA in the same board at a lower cost. In another embodiment, the I/O cells are mask programmable such that they can emulate the I/O characteristics of FPGAs from any of two or more FPGA families. This ability reduces the number of separate HardWire devices that must be designed, manufactured, tested, stored, and sold, and also simplifies the software required to convert designs to the new device. Some embodiments of the invention can also emulate other programmable devices such as PLDs.

摘要翻译： 提供了一种混合HardWire器件，其包括门阵列核心和一组具有类似于FPGA的I / O特性的掩码可编程I / O单元，即足够相同，因此HardWire器件可以用作下拉电阻， 替代FPGA而不重新设计原始系统。 使用这种HardWire设备，最初在FPGA中实现的用户设计可以在HardWire设备中进行仿真，然后以较低的成本替换同一块电路板中的FPGA。 在另一个实施例中，I / O单元是掩模可编程的，使得它们可以从两个或多个FPGA系列中的任何一个模拟FPGA的I / O特性。 这种能力减少了必须设计，制造，测试，存储和销售的单独的HardWire设备的数量，还简化了将设计转换为新设备所需的软件。 本发明的一些实施例还可以模拟其他可编程设备，例如PLD。

公开(公告)号：US5991908A

公开(公告)日：1999-11-23

申请号：US939757

申请日：1997-09-29

申请人： Glenn A. Baxter ,  Kiran B. Buch ,  Raymond C. Pang ,  Edwin S. Law

发明人： Glenn A. Baxter ,  Kiran B. Buch ,  Raymond C. Pang ,  Edwin S. Law

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318519

摘要： A programmable IC is provided that includes dedicated boundary scan logic having a programmable boundary scan bit-order. Boundary scan cells are provided, each cell being capable of providing the boundary scan functions associated with one I/O pad. In a mask programmable device, dedicated tracks are provided for adding mask programmable interconnect lines. In other programmable ICs such as FPGAs or PLDs, programmable interconnect lines are provided. In either case, the interconnect lines are used to implement the boundary scan data chain. Using these lines, the programmed device can "swap the order" of I/O cells in the boundary scan data chain, or leave cells out of the chain entirely. In one embodiment, the interconnect lines traverse each cell, programmably connecting the data inputs and outputs of adjacent or non-adjacent boundary scan cells. In other embodiments, the interconnect lines are physically located outside the boundary scan cells, either in a ring between the cell and the core or in the core itself.

摘要翻译： 提供了一种可编程IC，其包括具有可编程边界扫描比特顺序的专用边界扫描逻辑。 提供了边界扫描单元，每个单元能够提供与一个I / O垫相关联的边界扫描功能。 在掩模可编程设备中，提供专用轨道用于添加掩模可编程互连线。 在其他可编程IC（例如FPGA或PLD）中，提供可编程互连线。 在任一情况下，互连线用于实现边界扫描数据链。 使用这些线路，编程设备可以在边界扫描数据链中“交换I / O单元”的顺序，或将单元格完全从链中留出。 在一个实施例中，互连线穿过每个单元，可编程地连接相邻或非相邻边界扫描单元的数据输入和输出。 在其他实施例中，互连线物理地位于边界扫描单元外部，无论是在单元和芯之间的环中还是在芯本身中。

公开(公告)号：US06226779B1

公开(公告)日：2001-05-01

申请号：US09546461

申请日：2000-04-10

申请人： Glenn A. Baxter ,  Kiran B. Buch ,  Edwin S. Law

发明人： Glenn A. Baxter ,  Kiran B. Buch ,  Edwin S. Law

IPC分类号： G06F1127

CPC分类号： G01R31/318583

摘要： A mask programmable IC is provided that includes dedicated boundary scan logic in the I/O cells. Valuable core logic resources therefore need not be consumed to implement boundary scan logic. In one embodiment, one boundary scan cell is provided per I/O cell. Another embodiment provides great flexibility in emulating any of several FPGAs in any of several packages. In this embodiment, two boundary scan cells are provided for each I/O pad, each cell alone being capable of providing the boundary scan functions associated with one I/O pad. By selectively choosing which of the boundary scan cells are included in the boundary scan data chain, the order of the boundary scan chain of the emulated FPGA in any of two or more packages can be reproduced. Boundary scan behavior is therefore emulated as well as the programmable logic behavior of the FPGA. In one embodiment, additional programmable interconnect lines traversing each boundary scan cell are provided. These interconnect lines can be used to programmably connect the data output of a first cell to the data input of second cell which need not be adjacent to the first.

摘要翻译： 提供了一种掩模可编程IC，其包括I / O单元中的专用边界扫描逻辑。 因此，不需要消耗有价值的核心逻辑资源来实现边界扫描逻辑。 在一个实施例中，每个I / O单元提供一个边界扫描单元。 另一个实施例提供了极大的灵活性来模拟几个封装中的任何一个中的几个FPGA中的任何一个。 在该实施例中，为每个I / O焊盘提供两个边界扫描单元，每个单元仅能够提供与一个I / O焊盘相关联的边界扫描功能。 通过选择性地选择边界扫描单元中的哪一个被包括在边界扫描数据链中，可以再现两个或更多个包中的任一个中的仿真FPGA的边界扫描链的顺序。 因此，边界扫描行为以及FPGA的可编程逻辑行为。 在一个实施例中，提供穿过每个边界扫描单元的附加可编程互连线。 这些互连线可用于将第一单元的数据输出可编程地连接到不需要与第一单元相邻的第二单元的数据输入。

公开(公告)号：US6071314A

公开(公告)日：2000-06-06

申请号：US940154

申请日：1997-09-29

申请人： Glenn A. Baxter ,  Kiran B. Buch ,  Edwin S. Law

发明人： Glenn A. Baxter ,  Kiran B. Buch ,  Edwin S. Law

IPC分类号： G01R31/3185 ,  G06F11/27 ,  G01R31/3187 ,  G06F17/50

CPC分类号： G01R31/318583

摘要： A mask programmable IC is provided that includes dedicated boundary scan logic in the I/O cells. Valuable core logic resources therefore need not be consumed to implement boundary scan logic. In one embodiment, one boundary scan cell is provided per I/O cell. Another embodiment provides great flexibility in emulating any of several FPGAs in any of several packages. In this embodiment, two boundary scan cells are provided for each I/O pad, each cell alone being capable of providing the boundary scan functions associated with one I/O pad. By selectively choosing which of the boundary scan cells are included in the boundary scan data chain, the order of the boundary scan chain of the emulated FPGA in any of two or more packages can be reproduced. Boundary scan behavior is therefore emulated as well as the programmable logic behavior of the FPGA. In one embodiment, additional programmable interconnect lines traversing each boundary scan cell are provided. Theses interconnect lines can be used to programmably connect the data output of a first cell to the data input of second cell which need not be adjacent to the first.

摘要翻译： 提供了一种掩模可编程IC，其包括I / O单元中的专用边界扫描逻辑。 因此，不需要消耗有价值的核心逻辑资源来实现边界扫描逻辑。 在一个实施例中，每个I / O单元提供一个边界扫描单元。 另一个实施例提供了极大的灵活性来模拟几个封装中的任何一个中的几个FPGA中的任何一个。 在该实施例中，为每个I / O焊盘提供两个边界扫描单元，每个单元仅能够提供与一个I / O焊盘相关联的边界扫描功能。 通过选择性地选择边界扫描单元中的哪一个被包括在边界扫描数据链中，可以再现两个或更多个包中的任一个中的仿真FPGA的边界扫描链的顺序。 因此，边界扫描行为以及FPGA的可编程逻辑行为。 在一个实施例中，提供穿过每个边界扫描单元的附加可编程互连线。 这些互连线可以用于将第一单元的数据输出可编程地连接到不需要与第一单元相邻的第二单元的数据输入。

公开(公告)号：US5550839A

公开(公告)日：1996-08-27

申请号：US30981

申请日：1993-03-12

申请人： Kiran B. Buch ,  Edwin S. Law ,  Jakong J. Chu

发明人： Kiran B. Buch ,  Edwin S. Law ,  Jakong J. Chu

IPC分类号： G06F11/22 ,  G01R31/3185 ,  G06F11/26 ,  G06F17/50 ,  H01L21/82 ,  G01R31/28

CPC分类号： G01R31/318519 ,  G06F11/261 ,  G06F17/5068 ,  Y10S706/921

摘要： Method and apparatus for producing mask-configured integrated circuits which are pin, logic, and timing compatible substitutes for user-configured logic arrays, without the need for logic or timing simulations of the mask-configured circuit design. Scan testing networks of test blocks and modified flip flops are included in the mask-configured substitutes to test functionality. Logic compatibility to the user-configured logic array (an FPGA) is preserved by clustering together in the mask-configured integrated circuit (a gate array) all of the logic gates which perform the functions of a particular FPGA logic block. Moreover, only those FPGA logic gates or functions which are used are replicated in the gate array, to conserve chip area. Test blocks are inserted in the gate array only where needed, i.e. at the output of any function generator that has connections external to the configurable logic block, and all flip flops are modified to also function as test blocks in a test mode. All logic blocks along asynchronous data paths in the FPGA are timing matched by delay elements in the mask-programmed substitute to preserve timing compatibility to the FPGA.

摘要翻译： 用于生产掩模配置集成电路的方法和装置，其是针对用户配置的逻辑阵列的引脚，逻辑和时序兼容的替代，而不需要对掩模配置的电路设计进行逻辑或定时仿真。 测试块和修改的触发器的扫描测试网络包含在掩模配置的替代测试功能中。 通过在执行特定FPGA逻辑块功能的所有逻辑门的掩模配置集成电路（门阵列）中聚集在一起，保留了与用户配置的逻辑阵列（FPGA）的逻辑兼容性。 此外，仅在门阵列中复制所使用的那些FPGA逻辑门或功能，以节省芯片面积。 测试块仅在需要时插入门阵列中，即在可配置逻辑块外部具有连接的任何函数发生器的输出端，并且所有触发器被修改为在测试模式中也用作测试块。 沿着FPGA中的异步数据路径的所有逻辑块都通过掩码编程的替代中的延迟元件进行定时匹配，以保持与FPGA的时序兼容性。

公开(公告)号：US6070260A

公开(公告)日：2000-05-30

申请号：US156534

申请日：1998-09-17

申请人： Kiran B. Buch ,  Mehul R. Vashi

发明人： Kiran B. Buch ,  Mehul R. Vashi

IPC分类号： G01R31/317 ,  G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/31725 ,  G01R31/318552 ,  G01R31/318594

摘要： A method is provided for scan testing that eliminates the need for balancing internal scan clock delays. According to the method of the invention, multiple scan clocks are provided, each being provided to a different set of flip-flops. The skew between the active edges of the scan clocks is deliberately increased to the point where each set of flip-flops has plenty of time to settle before the next set of flip-flops receives a clock pulse. Because scan testing is typically performed at clock speeds of only about 1 Megahertz, there is time for each of the scan clocks to pulse separately from all the others, without increasing the test time. The increased delay between scan clock pulses eliminates the need for balancing internal delays on the scan clock paths, thereby greatly reducing the number of placement and routing iterations required to achieve a functional design.

摘要翻译： 提供了一种用于扫描测试的方法，无需平衡内部扫描时钟延迟。 根据本发明的方法，提供了多个扫描时钟，每个扫描时钟被提供给不同的触发器组。 扫描时钟的有效边沿之间的偏斜有意增加到每组触发器在下一组触发器接收时钟脉冲之前具有足够的时间来稳定的点。 因为扫描测试通常以仅约1兆赫的时钟速度进行，所以每个扫描时钟都有时间与所有其他扫描时钟分开脉冲，而不增加测试时间。 扫描时钟脉冲之间的增加的延迟消除了平衡扫描时钟路径上的内部延迟的需要，从而大大减少了实现功能设计所需的放置次数和路由迭代次数。