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公开(公告)号：US06353921B1
公开(公告)日：2002-03-05
申请号：US09560438
申请日：2000-04-28
申请人： Edwin S. Law , Kiran B. Buch , Glenn A. Baxter , Raymond C. Pang
发明人： Edwin S. Law , Kiran B. Buch , Glenn A. Baxter , Raymond C. Pang
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： A hybrid HardWire device is provided that comprises a gate array core and a set of mask programmable I/O cells having I/O characteristics similar to those of an FPGA, i.e., sufficiently the same so the HardWire device can be used as a drop-in replacement for the FPGA with no redesign of the original system. Using this HardWire device, a user's design originally implemented in an FPGA can be emulated in the HardWire device, which then replaces the FPGA in the same board at a lower cost. In another embodiment, the I/O cells are mask programmable such that they can emulate the I/O characteristics of FPGAs from any of two or more FPGA families. This ability reduces the number of separate HardWire devices that must be designed, manufactured, tested, stored, and sold, and also simplifies the software required to convert designs to the new device. Some embodiments of the invention can also emulate other programmable devices such as PLDs.
摘要翻译： 提供了一种混合HardWire器件，其包括门阵列核心和一组具有类似于FPGA的I / O特性的掩码可编程I / O单元，即足够相同，因此HardWire器件可以用作下拉电阻， 替代FPGA而不重新设计原始系统。 使用这种HardWire设备，最初在FPGA中实现的用户设计可以在HardWire设备中进行仿真，然后以较低的成本替换同一块电路板中的FPGA。 在另一个实施例中，I / O单元是掩模可编程的，使得它们可以从两个或多个FPGA系列中的任何一个模拟FPGA的I / O特性。 这种能力减少了必须设计，制造，测试，存储和销售的单独的HardWire设备的数量，还简化了将设计转换为新设备所需的软件。 本发明的一些实施例还可以模拟其他可编程设备，例如PLD。
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公开(公告)号：US6134517A
公开(公告)日：2000-10-17
申请号：US384714
申请日：1999-08-26
申请人： Glenn A. Baxter , Kiran B. Buch , Raymond C. Pang , Edwin S. Law
发明人： Glenn A. Baxter , Kiran B. Buch , Raymond C. Pang , Edwin S. Law
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318519
摘要： A method of implementing a boundary scan chain is provided using a programmable IC that includes dedicated boundary scan logic having a programmable boundary scan bit-order. Boundary scan cells are provided, each cell being capable of providing the boundary scan functions associated with one I/O pad. In a mask programmable device, dedicated tracks are provided for adding mask programmable interconnect lines. In other programmable ICs such as FPGAs or PLDs, programmable interconnect lines are provided. In either case, the interconnect lines are used to implement the boundary scan data chain. Using these lines, the programmed device can "swap the order" of I/O cells in the boundary scan data chain, or leave cells out of the chain entirely. In one embodiment, the interconnect lines traverse each cell, programmably connecting the data inputs and outputs of adjacent or non-adjacent boundary scan cells. In other embodiments, the interconnect lines are physically located outside the boundary scan cells, either in a ring between the cell and the core or in the core itself.
摘要翻译： 使用包括具有可编程边界扫描位顺序的专用边界扫描逻辑的可编程IC来提供实现边界扫描链的方法。 提供了边界扫描单元，每个单元能够提供与一个I / O垫相关联的边界扫描功能。 在掩模可编程设备中，提供专用轨道用于添加掩模可编程互连线。 在其他可编程IC（例如FPGA或PLD）中，提供可编程互连线。 在任一情况下，互连线用于实现边界扫描数据链。 使用这些线路，编程设备可以在边界扫描数据链中“交换I / O单元”的顺序，或将单元格完全从链中留出。 在一个实施例中，互连线穿过每个单元，可编程地连接相邻或非相邻边界扫描单元的数据输入和输出。 在其他实施例中，互连线物理地位于边界扫描单元外部，无论是在单元和芯之间的环中还是在芯本身中。
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公开(公告)号：US6120551A
公开(公告)日：2000-09-19
申请号：US937809
申请日：1997-09-29
申请人： Edwin S. Law , Kiran B. Buch , Glenn A. Baxter , Raymond C. Pang
发明人： Edwin S. Law , Kiran B. Buch , Glenn A. Baxter , Raymond C. Pang
CPC分类号： G06F17/5045
摘要： A hybrid HardWire device is provided that comprises a gate array core and a set of mask programmable I/O cells having I/O characteristics similar to those of an FPGA, i.e., sufficiently the same so the HardWire device can be used as a drop-in replacement for the FPGA with no redesign of the original system. Using this HardWire device, a user's design originally implemented in an FPGA can be emulated in the HardWire device, which then replaces the FPGA in the same board at a lower cost. In another embodiment, the I/O cells are mask programmable such that they can emulate the I/O characteristics of FPGAs from any of two or more FPGA families. This ability reduces the number of separate HardWire devices that must be designed, manufactured, tested, stored, and sold, and also simplifies the software required to convert designs to the new device. Some embodiments of the invention can also emulate other programmable devices such as PLDs.
摘要翻译： 提供了一种混合HardWire器件，其包括门阵列核心和一组具有类似于FPGA的I / O特性的掩码可编程I / O单元，即足够相同，因此HardWire器件可以用作下拉电阻， 替代FPGA而不重新设计原始系统。 使用这种HardWire设备，最初在FPGA中实现的用户设计可以在HardWire设备中进行仿真，然后以较低的成本替换同一块电路板中的FPGA。 在另一个实施例中，I / O单元是掩模可编程的，使得它们可以从两个或多个FPGA系列中的任何一个模拟FPGA的I / O特性。 这种能力减少了必须设计，制造，测试，存储和销售的单独的HardWire设备的数量，还简化了将设计转换为新设备所需的软件。 本发明的一些实施例还可以模拟其他可编程设备，例如PLD。
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公开(公告)号：US5991908A
公开(公告)日：1999-11-23
申请号：US939757
申请日：1997-09-29
申请人： Glenn A. Baxter , Kiran B. Buch , Raymond C. Pang , Edwin S. Law
发明人： Glenn A. Baxter , Kiran B. Buch , Raymond C. Pang , Edwin S. Law
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318519
摘要： A programmable IC is provided that includes dedicated boundary scan logic having a programmable boundary scan bit-order. Boundary scan cells are provided, each cell being capable of providing the boundary scan functions associated with one I/O pad. In a mask programmable device, dedicated tracks are provided for adding mask programmable interconnect lines. In other programmable ICs such as FPGAs or PLDs, programmable interconnect lines are provided. In either case, the interconnect lines are used to implement the boundary scan data chain. Using these lines, the programmed device can "swap the order" of I/O cells in the boundary scan data chain, or leave cells out of the chain entirely. In one embodiment, the interconnect lines traverse each cell, programmably connecting the data inputs and outputs of adjacent or non-adjacent boundary scan cells. In other embodiments, the interconnect lines are physically located outside the boundary scan cells, either in a ring between the cell and the core or in the core itself.
摘要翻译： 提供了一种可编程IC，其包括具有可编程边界扫描比特顺序的专用边界扫描逻辑。 提供了边界扫描单元，每个单元能够提供与一个I / O垫相关联的边界扫描功能。 在掩模可编程设备中，提供专用轨道用于添加掩模可编程互连线。 在其他可编程IC（例如FPGA或PLD）中，提供可编程互连线。 在任一情况下，互连线用于实现边界扫描数据链。 使用这些线路，编程设备可以在边界扫描数据链中“交换I / O单元”的顺序，或将单元格完全从链中留出。 在一个实施例中，互连线穿过每个单元，可编程地连接相邻或非相邻边界扫描单元的数据输入和输出。 在其他实施例中，互连线物理地位于边界扫描单元外部，无论是在单元和芯之间的环中还是在芯本身中。
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公开(公告)号：US07515452B1
公开(公告)日：2009-04-07
申请号：US11649447
申请日：2007-01-03
IPC分类号： G11C11/00
CPC分类号： G11C8/04 , H03K19/00392 , H03K19/1776 , H03K19/17764 , H03K19/1778
摘要： A memory array has a first memory cell with a plurality of transistors connected so as to restore a data value to a node of the memory cell to an initial value following an event upsetting the initial value. A first portion of the plurality of transistors is in a first cell portion and a second portion of the plurality of transistors is in a second cell portion. A second memory cell has a third cell portion and a fourth cell portion. The third cell portion is between the first cell portion and the second cell portion and adjacent to each of the first cell portion and the second cell portion. In a particular embodiment, the memory cell is a single-event-upset (“SEU”) tolerant memory cell and the first and second cell portions are each a half cell of a sixteen transistor memory cell.
摘要翻译： 存储器阵列具有连接有多个晶体管的第一存储器单元，以便在事件颠倒初始值之后将数据值恢复到存储器单元的节点到初始值。 多个晶体管的第一部分在第一单元部分中，并且多个晶体管的第二部分在第二单元部分中。 第二存储单元具有第三单元部分和第四单元部分。 第三单元部分在第一单元部分和第二单元部分之间并且与第一单元部分和第二单元部分中的每一个相邻。 在特定实施例中，存储器单元是单事件不正常（“SEU”）容限存储器单元，并且第一和第二单元部分各自是十六晶体管存储单元的半单元。
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6.发明授权Methods of providing families of integrated circuits with similar dies partially disabled using product selection codes 有权使用产品选择代码为集成电路系列提供类似模具的方法部分禁用公开(公告)号：US07402443B1
公开(公告)日：2008-07-22
申请号：US11333819
申请日：2006-01-17
IPC分类号： G01R31/26
CPC分类号： H01L27/11807 , H01L27/0207
摘要： A method of providing a family of integrated circuits (ICs) includes applying a first product selection code (PSC) to a first IC die, applying a second PSC to a second IC die, and providing a third packaged IC die. The first IC die includes first and second portions, both of which are operational based on the first PSC. The second IC die is a duplicate of the first die, but the second portion is rendered non-operational by the second PSC. The third IC die is substantially similar to the first portion of the first die. The second and third packages can be the same and the packaged dies can be interchangeable in a system. When the dies are programmable logic device (PLD) dies, the second and third dies use the same configuration bit stream, which may be smaller than the configuration bit stream for the first IC die.
摘要翻译： 提供集成电路（IC）系列的方法包括：将第一产品选择代码（PSC）应用于第一IC芯片，将第二PSC应用于第二IC芯片，以及提供第三封装IC芯片。 第一IC芯片包括第一和第二部分，它们都基于第一PSC而可操作。 第二IC芯片是第一裸片的副本，但是第二部分由第二PSC不可操作。 第三IC管芯基本上类似于第一管芯的第一部分。 第二和第三包可以是相同的，并且包装的模具可以在系统中互换。 当管芯是可编程逻辑器件（PLD）管芯时，第二和第三管芯使用与第一IC管芯的配置位流相同的配置位流。
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公开(公告)号：US07157951B1
公开(公告)日：2007-01-02
申请号：US10837186
申请日：2004-04-30
申请人： Shawn K. Morrison , Raymond C. Pang
发明人： Shawn K. Morrison , Raymond C. Pang
IPC分类号： H03H11/26
CPC分类号： H03K5/15013 , G06F1/10
摘要： A delay line for a digital clock manager includes a tap delay structure and a trim delay structure. The trim delay structure includes a first buffer coupled to receive a clock signal from the tap delay structure, and in response, provide a delayed clock signal to a set of clock lines. The trim delay structure also includes a capacitive trim unit having a plurality of capacitive trim elements tapped off the set of clock lines. The capacitive trim elements are selectively enabled or disabled, thereby introducing additional delay to the delayed clock signal on the set of clock lines. Each capacitive trim element can include a transmission gate structure, which is turned on to introduce significant junction capacitance to the set of clock lines. The trim delay structure can also include a second buffer adapted to buffer the delayed clock signal on the set of clock lines.
摘要翻译： 数字时钟管理器的延迟线包括抽头延迟结构和修整延迟结构。 修剪延迟结构包括第一缓冲器，其被耦合以从抽头延迟结构接收时钟信号，并且作为响应，向一组时钟线提供延迟的时钟信号。 修剪延迟结构还包括电容修剪单元，其具有从该组时钟线分离的多个电容修剪元件。 电容调整元件被选择性地使能或禁止，从而对该组时钟线上的延迟的时钟信号引入额外的延迟。 每个电容调整元件可以包括传输门结构，其被导通以将显着的结电容引入该组时钟线。 修剪延迟结构还可以包括适于缓冲该组时钟线上延迟的时钟信号的第二缓冲器。
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公开(公告)号：US06981153B1
公开(公告)日：2005-12-27
申请号：US09724975
申请日：2000-11-28
CPC分类号： H04N21/23476 , G06F17/5054 , G06F21/76
摘要： It is sometimes desirable to protect a design used in a PLD from being copied. If the design is stored in a different device from the PLD and read into the PLD through a bitstream, the design may be encrypted as it is read into the PLD and decrypted within the PLD before being loaded into configuration memory cells for configuring the PLD. According to the invention, in such a device, a method is provided to prevent the design from being read back from the PLD in its decrypted state if it had been encrypted when loaded into the PLD.
摘要翻译： 有时期望保护PLD中使用的设计不被复制。 如果设计存储在与PLD不同的设备中并且通过比特流读入PLD，则在加载到用于配置PLD的配置存储器单元之前，设计可以在PLD中被读入PLD并被解密并被解密。 根据本发明，在这种设备中，提供了一种方法，用于防止在被加载到PLD中时将设计从PLD解密的状态下读回PLD。
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公开(公告)号：US06282127B1
公开(公告)日：2001-08-28
申请号：US09625672
申请日：2000-07-24
IPC分类号： G11C700
CPC分类号： G11C7/1051 , G11C7/1057
摘要： A RAM block includes a circuit for causing the RAM to provide a reset value on the output or a previously captured output value from the RAM when a Reset signal is active. The Reset signal does not change the RAM contents but causes all outputs of the block RAM to be either a reset value or a capture value, as selected by the user. This is useful when the RAM block is configured as a state machine. Thus, in an FPGA or other programmable device, an application can start the state machine in a known state with all address bits equal to 0 and can reset the state machine to this startup state. When the reset signal is active, the state machine can feed back the reset value or capture value to the address inputs of the RAM block that receive state feedback data, regardless of the data actually in those locations.
摘要翻译： RAM块包括用于当复位信号有效时使RAM在输出上提供复位值或从RAM提供先前捕获的输出值的电路。 复位信号不会更改RAM内容，但会导致块RAM的所有输出为用户选择的复位值或捕捉值。 当RAM块被配置为状态机时，这是有用的。 因此，在FPGA或其他可编程器件中，应用程序可以在所有地址位等于0的已知状态下启动状态机，并可将状态机复位到该启动状态。 当复位信号有效时，状态机可以将接收状态反馈数据的复位值或捕获值反馈给RAM块的地址输入，无论这些位置中的数据如何。
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公开(公告)号：US07501879B1
公开(公告)日：2009-03-10
申请号：US11717836
申请日：2007-03-13
申请人： Kwansuhk Oh , Raymond C. Pang , Hsung Jai Im , Sunhom Paak
发明人： Kwansuhk Oh , Raymond C. Pang , Hsung Jai Im , Sunhom Paak
摘要： An eFuse sensing circuit replaces the inverters used to provide the “read” output state of a conventional eFuse circuit. The sensing circuit includes a comparator with one input coupled to the eFuse circuitry, and a second input coupled to a reference voltage generator circuit. The reference voltage generator circuit includes an internal resistor. Transistors of the sense circuit are provided to mimic the transistors of the eFuse circuit, so that variations of transistors due to process, voltage and temperature will be substantially the same. The resistor of the sense circuit is then effectively compared with the resistance of the eFuse by the comparator irrespective of temperature and process variations.
摘要翻译： eFuse感测电路取代了用于提供常规eFuse电路的“读取”输出状态的逆变器。 感测电路包括具有耦合到eFuse电路的一个输入和耦合到参考电压发生器电路的第二输入的比较器。 参考电压发生器电路包括内部电阻器。 提供感测电路的晶体管以模拟eFuse电路的晶体管，使得由于工艺，电压和温度而导致的晶体管的变化将基本相同。 然后将感测电路的电阻与比较器的eFuse的电阻进行有效的比较，而与温度和工艺变化无关。
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