公开(公告)号：US11763386B2

公开(公告)日：2023-09-19

申请号：US18045104

申请日：2022-10-07

Applicant: REBELLIONS INC.

Inventor： Hyunsung Kim ,  Sungyeob Yoo ,  Sunghyun Park ,  Jinwook Oh

IPC: G06Q40/00 ,  G06Q40/04 ,  G06Q30/0202

CPC classification number: G06Q40/04 ,  G06Q30/0202

Abstract: The disclosure relates to an apparatus for high frequency trading. The apparatus includes one or more memories, at least one reconfigurable processor coupled to the one or more memories, and a dedicated accelerator preconfigured for the machine learning model. The one or more processors receive market-related information from one or more market-related information servers and generates market prediction reference data based on the market-related information. The dedicated accelerator performs operations for the machine learning model with the market prediction reference data to generate future market prediction data. The at least one reconfigurable processor generates an order signal based on the future market prediction data and transmits the order signal to a target exchange server.

公开(公告)号：US20230161480A1

公开(公告)日：2023-05-25

申请号：US18046100

申请日：2022-10-12

Applicant: Rebellions Inc.

Inventor： Wongyu Shin ,  Jinwook Oh

IPC: G06F3/06 ,  G06N3/08 ,  G06N3/063

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673 ,  G06N3/08 ,  G06N3/063

Abstract: A reconfigurable on-chip memory bank, reconfigurable on-chip memory, system-on-chip having same mounted thereon, and method for using reconfigurable on-chip memory is provided. The reconfigurable on-chip memory bank comprises a cell array in which a plurality of cells are arranged and data are stored, a first path unit configured to move data in the cell array, a second path unit configured to move data in the cell array and a bank controller operably coupled with the first and second path units, and configured to determine, according to a path control signal during runtime, data path which data are to be transmitted to or received from, to use a first address system when the first path unit is determined to be the data path, and to use a second address system different from the first address system when the second path unit is determined to be the data path.

公开(公告)号：US20230153906A1

公开(公告)日：2023-05-18

申请号：US18045104

申请日：2022-10-07

Applicant: REBELLIONS INC.

Inventor： Hyunsung Kim ,  Sungyeob Yoo ,  Sunghyun Park ,  Jinwook Oh

IPC: G06Q40/04 ,  G06Q30/0202

CPC classification number: G06Q40/04 ,  G06Q30/0202

Abstract: The disclosure relates to an apparatus for high frequency trading. The apparatus includes one or more memories, at least one reconfigurable processor coupled to the one or more memories, and a dedicated accelerator preconfigured for the machine learning model. The one or more processors receive market-related information from one or more market-related information servers and generates market prediction reference data based on the market-related information. The dedicated accelerator performs operations for the machine learning model with the market prediction reference data to generate future market prediction data. The at least one reconfigurable processor generates an order signal based on the future market prediction data and transmits the order signal to a target exchange server.

公开(公告)号：US20230140309A1

公开(公告)日：2023-05-04

申请号：US17938024

申请日：2022-10-04

Applicant: Rebellions Inc.

Inventor： Jinwook Oh ,  Jinseok Kim ,  Donghan Kim ,  Kyeongryeol Bong

IPC: G06F12/0875 ,  G06N3/04 ,  G06F9/30

Abstract: A neural processing device is provided. The neural processing device comprises: a processing unit configured to receive an input activation and a weight and perform a two-dimensional matrix calculation with the input activation and the weight to generate an output activation, a first memory, and a load-store unit (LSU) configured to perform memory access operations between the first memory and a second memory. The memory access operations include a main memory access operation for a current processing operation that is performed by the processing unit, and a standby memory access operation for a standby processing operation that is performed by the processing unit after the current processing operation. A level of the first memory is equal to a level of the processing unit, and a level of the second memory is different from the level of the first memory.

公开(公告)号：US12229829B2

公开(公告)日：2025-02-18

申请号：US18365945

申请日：2023-08-04

Applicant: REBELLIONS INC.

Inventor： Hyunsung Kim ,  Sungyeob Yoo ,  Sunghyun Park ,  Jinwook Oh

IPC: G06Q40/00 ,  G06Q30/0202 ,  G06Q40/04

Abstract: The disclosure relates to an apparatus for high frequency trading. The apparatus includes one or more memories, at least one reconfigurable processor coupled to the one or more memories, and a dedicated accelerator preconfigured for the machine learning model. The one or more processors receive market-related information from one or more market-related information servers and generates market prediction reference data based on the market-related information. The dedicated accelerator performs operations for the machine learning model with the market prediction reference data to generate future market prediction data. The at least one reconfigurable processor generates an order signal based on the future market prediction data and transmits the order signal to a target exchange server.

公开(公告)号：US12210872B2

公开(公告)日：2025-01-28

申请号：US18602924

申请日：2024-03-12

Applicant: Rebellions Inc.

Inventor： Karim Charfi ,  Jinwook Oh

IPC: G06F9/30 ,  G06F9/38

Abstract: A neural processing device, a processing element included therein and a method for operating various formats of the neural processing device are provided. The neural processing device includes at least one neural processor, a shared memory shared by the at least one neural processor, and a global interconnection configured to transmit data between the at least one neural processor and the shared memory, wherein each of the at least one neural processor comprises at least one processing element, each of the at least one processing element receives an input in a first format and thereby performs an operation, and receives an input in a second format that is different from the first format and thereby performs an operation if a format conversion signal is received, and the first format and the second format have a same number of bits.

公开(公告)号：US12197886B2

公开(公告)日：2025-01-14

申请号：US18191737

申请日：2023-03-28

Applicant: Rebellions Inc.

Inventor： Jinwook Oh

IPC: G06F5/00 ,  G06F3/06 ,  G06F5/06

Abstract: A neural processing device and a method for converting data thereof are provided. The neural processing device comprises a first compute unit configured to receive first input data in first precision and generate first output data in the first precision by performing calculations, a second compute unit configured to receive second input data in second precision which is different from the first precision and generate second output data in the second precision by performing calculation, and a first converting buffer configured to receive and store the first output data, generate the second input data by converting the first output data into the second precision, and transmit the second input data to the second compute unit.

公开(公告)号：US12118616B2

公开(公告)日：2024-10-15

申请号：US18494703

申请日：2023-10-25

Applicant: REBELLIONS INC.

Inventor： Hyunsung Kim ,  Sungyeob Yoo ,  Jinwook Oh

IPC: G06Q40/04

CPC classification number: G06Q40/04

Abstract: A method for adjusting a hardware performance for high frequency trading is provided, which is performed by one or more processors, and includes receiving context information including at least one of a traffic of market data for one or more target items or a computational complexity of using a machine learning model performed based on the market data, determining whether or not to change a processing performance of the hardware based on the received context information, and changing a resource supplied to the hardware based on the determination result for changing the processing performance.

公开(公告)号：US20240320059A1

公开(公告)日：2024-09-26

申请号：US18389680

申请日：2023-12-19

Applicant: REBELLIONS INC.

Inventor： Hyunho Kim ,  Jinseok Kim ,  Jinwook Oh

IPC: G06F9/50

CPC classification number: G06F9/5083

Abstract: A method for processing tasks in parallel is performed by at least one processor, and includes performing a first task associated with a first instruction, determining whether the first instruction is a burst load instruction, in response to determining that the first instruction is the burst load instruction, acquiring a second instruction, and performing a second task associated with the acquired second instruction, in which the first task and the second task are performed in parallel.

公开(公告)号：US12079661B2

公开(公告)日：2024-09-03

申请号：US18491695

申请日：2023-10-20

Applicant: Rebellions Inc.

Inventor： Wongyu Shin ,  Miock Chi ,  Hongyun Kim ,  Jinwook Oh ,  Juyeong Yoon

IPC: G06F9/48 ,  G06F9/38

CPC classification number: G06F9/4881 ,  G06F9/3838

Abstract: A neural processing device and a method for managing tasks thereof are provided. The neural processing device includes a neural core configured to perform a task and generate a completion signal for completion of the task, a core global configured to transfer task information for the task to the neural core and receive the completion signal of the task from the neural core, and a task manager configured to generate and transmit the task information to the core global, receive the completion signal from the core global, generate a completion report, and transmit the completion report.