公开(公告)号：US07166521B2

公开(公告)日：2007-01-23

申请号：US10957833

申请日：2004-10-04

申请人： Diane C. Boyd ,  Hussein I. Hanafi ,  Erin C. Jones ,  Dominic J. Schepis ,  Leathen Shi

发明人： Diane C. Boyd ,  Hussein I. Hanafi ,  Erin C. Jones ,  Dominic J. Schepis ,  Leathen Shi

IPC分类号： H01L21/30 ,  H01L21/46 ,  H01L21/21 ,  H01L21/36 ,  H01L21/425

CPC分类号： H01L21/76251 ,  H01L21/76243

摘要： A method of fabricating a SOI wafer having a gate-quality, thin buried oxide region is provided. The wafer is fabricating by forming a substantially uniform thermal oxide on a surface of a Si-containing layer of a SOI substrate which includes a buried oxide region positioned between the Si-containing layer and a Si-containing substrate layer. Next, a cleaning process is employed to form a hydrophilic surface on the thermal oxide. A carrier wafer having a hydrophilic surface is provided and positioned near the substrate such that the hydrophilic surfaces adjoin each other. Room temperature bonding is then employed to bond the carrier wafer to the substrate. An annealing step is performed and thereafter, the Si-containing substrate of the silicon-on-insulator substrate and the buried oxide region are selectively removed to expose the Si-containing layer.

摘要翻译： 提供一种制造具有栅极质量薄的掩埋氧化物区域的SOI晶片的方法。 通过在SOI衬底的含Si层的表面上形成基本上均匀的热氧化物来制造晶片，该衬底包括位于含Si层和含Si衬底层之间的掩埋氧化物区域。 接下来，使用清洁方法在热氧化物上形成亲水性表面。 提供具有亲水表面的载体晶片并且将其定位在基板附近，使得亲水表面彼此相邻。 然后使用室温粘合将载体晶片粘合到基底上。 进行退火工序，然后选择性地除去绝缘体上硅衬底的含硅衬底和掩埋氧化物区域以暴露含Si层。

公开(公告)号：US07075150B2

公开(公告)日：2006-07-11

申请号：US10725849

申请日：2003-12-02

申请人： Diane C. Boyd ,  Bruce B. Doris ,  Meikei Ieong ,  Devendra K. Sadana

发明人： Diane C. Boyd ,  Bruce B. Doris ,  Meikei Ieong ,  Devendra K. Sadana

IPC分类号： H01L27/01

CPC分类号： H01L29/78696 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/78609 ,  H01L29/78684

摘要： The present invention provides a thin channel MOSFET having low external resistance. In broad terms, a silicon-on-insulator structure comprising a SOI layer located atop a buried insulating layer, said SOI layer having a channel region which is thinned by the presence of an underlying localized oxide region that is located on top of and in contact with said buried insulating layer; and a gate region located atop said SOI layer, wherein said localized oxide region is self-aligned with the gate region. A method for forming the inventive MOSFET is also provided comprising forming a dummy gate region atop a substrate; implanting oxide forming dopant through said dummy gate to create a localized oxide region in a portion of the substrate aligned to the dummy gate region that thins a channel region; forming source/drain extension regions abutting said channel region; and replacing the dummy gate with a gate conductor.

公开(公告)号：US06593617B1

公开(公告)日：2003-07-15

申请号：US09026093

申请日：1998-02-19

申请人： Diane C. Boyd ,  Stuart M. Burns ,  Hussein I. Hanafi ,  Yuan Taur ,  William C. Wille

发明人： Diane C. Boyd ,  Stuart M. Burns ,  Hussein I. Hanafi ,  Yuan Taur ,  William C. Wille

IPC分类号： H01L2976

CPC分类号： H01L29/66583

摘要： Metal oxide semiconductor field effect transistor (MOSFET) comprising a drain region and source region which enclose a channel region. A thin gate oxide is situated on the channel region and a gate conductor with vertical side walls is located on this gate oxide. The interfaces between the source region and channel region and the drain region and channel region are abrupt. Such an FET can be made using the following method: forming a dielectric stack on a semiconductor structure which at least comprises a pad oxide layer; defining an etch window having the lateral size and shape of a gate pillar to be formed; defining a gate hole in the dielectric stack by transferring the etch window into the dielectric stack using a reactive ion etching (RIE) process; depositing a gate conductor such that it fills the gate hole; removing the gate conductor covering the portions of the dielectric stack surrounding the gate hole; removing at least part of the dielectric stack such that a gate pillar with vertical side walls is set free.

摘要翻译： 金属氧化物半导体场效应晶体管（MOSFET）包括漏极区域和封装沟道区域的源极区域。 栅极氧化物位于通道区域上，并且具有垂直侧壁的栅极导体位于该栅极氧化物上。 源极区域和沟道区域以及漏极区域和沟道区域之间的界面是突然的。可以使用以下方法制造FET：在至少包括衬垫氧化物层的半导体结构上形成电介质堆叠;限定蚀刻 窗口，其具有要形成的门柱的横向尺寸和形状;通过使用反应离子蚀刻（RIE）工艺将蚀刻窗口转移到电介质堆叠中来在电介质堆叠中限定栅极孔;沉积栅极导体，使得其填充 栅极孔;去除覆盖围绕栅极孔的电介质堆叠的部分的栅极导体;去除至少部分介电堆叠，使得具有垂直侧壁的门柱被释放。