公开(公告)号：US07166521B2

公开(公告)日：2007-01-23

申请号：US10957833

申请日：2004-10-04

申请人： Diane C. Boyd ,  Hussein I. Hanafi ,  Erin C. Jones ,  Dominic J. Schepis ,  Leathen Shi

发明人： Diane C. Boyd ,  Hussein I. Hanafi ,  Erin C. Jones ,  Dominic J. Schepis ,  Leathen Shi

IPC分类号： H01L21/30 ,  H01L21/46 ,  H01L21/21 ,  H01L21/36 ,  H01L21/425

CPC分类号： H01L21/76251 ,  H01L21/76243

摘要： A method of fabricating a SOI wafer having a gate-quality, thin buried oxide region is provided. The wafer is fabricating by forming a substantially uniform thermal oxide on a surface of a Si-containing layer of a SOI substrate which includes a buried oxide region positioned between the Si-containing layer and a Si-containing substrate layer. Next, a cleaning process is employed to form a hydrophilic surface on the thermal oxide. A carrier wafer having a hydrophilic surface is provided and positioned near the substrate such that the hydrophilic surfaces adjoin each other. Room temperature bonding is then employed to bond the carrier wafer to the substrate. An annealing step is performed and thereafter, the Si-containing substrate of the silicon-on-insulator substrate and the buried oxide region are selectively removed to expose the Si-containing layer.

摘要翻译： 提供一种制造具有栅极质量薄的掩埋氧化物区域的SOI晶片的方法。 通过在SOI衬底的含Si层的表面上形成基本上均匀的热氧化物来制造晶片，该衬底包括位于含Si层和含Si衬底层之间的掩埋氧化物区域。 接下来，使用清洁方法在热氧化物上形成亲水性表面。 提供具有亲水表面的载体晶片并且将其定位在基板附近，使得亲水表面彼此相邻。 然后使用室温粘合将载体晶片粘合到基底上。 进行退火工序，然后选择性地除去绝缘体上硅衬底的含硅衬底和掩埋氧化物区域以暴露含Si层。

公开(公告)号：US06835633B2

公开(公告)日：2004-12-28

申请号：US10202329

申请日：2002-07-24

申请人： Diane C. Boyd ,  Hussein I. Hanafi ,  Erin C. Jones ,  Dominic J. Schepis ,  Leathen Shi

发明人： Diane C. Boyd ,  Hussein I. Hanafi ,  Erin C. Jones ,  Dominic J. Schepis ,  Leathen Shi

IPC分类号： H01L2176

CPC分类号： H01L21/76251 ,  H01L21/76243

摘要： A method of fabricating a SOI wafer having a gate-quality, thin buried oxide region is provided. The wafer is fabricating by forming a substantially uniform thermal oxide on a surface of a Si-containing layer of a SOI substrate which includes a buried oxide region positioned between the Si-containing layer and a Si-containing substrate layer. Next, a cleaning process is employed to form a hydrophilic surface on the thermal oxide. A carrier wafer having a hydrophilic surface is provided and positioned near the substrate such that the hydrophilic surfaces adjoin each other. Room temperature bonding is then employed to bond the carrier wafer to the substrate. An annealing step is performed and thereafter, the Si-containing substrate of the silicon-on-insulator substrate and the buried oxide region are selectively removed to expose the Si-containing layer.

摘要翻译： 提供一种制造具有栅极质量薄的掩埋氧化物区域的SOI晶片的方法。 通过在SOI衬底的含Si层的表面上形成基本上均匀的热氧化物来制造晶片，该衬底包括位于含Si层和含Si衬底层之间的掩埋氧化物区域。 接下来，使用清洁方法在热氧化物上形成亲水性表面。 提供具有亲水表面的载体晶片并且将其定位在基板附近，使得亲水表面彼此相邻。 然后使用室温粘合将载体晶片粘合到基底上。 进行退火工序，然后选择性地除去绝缘体上硅衬底的含硅衬底和掩埋氧化物区域以暴露含Si层。

公开(公告)号：US06660598B2

公开(公告)日：2003-12-09

申请号：US10084550

申请日：2002-02-26

申请人： Hussein I. Hanafi ,  Diane C. Boyd ,  Kevin K. Chan ,  Wesley Natzle ,  Leathen Shi

发明人： Hussein I. Hanafi ,  Diane C. Boyd ,  Kevin K. Chan ,  Wesley Natzle ,  Leathen Shi

IPC分类号： H01L21336

CPC分类号： H01L29/78696 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/78612

摘要： A sub-0.05 &mgr;m channel length fully-depleted SOI MOSFET device having low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. In accordance with the method of the present invention, at least one dummy gate region is first formed atop an SOI layer. The dummy gate region includes at least a sacrificial polysilicon region and first nitride spacers located on sidewalls of the sacrificial polysilicon region. Next, an oxide layer that is coplanar with an upper surface of the dummy gate region is formed and then the sacrificial polysilicon region is removed to expose a portion of the SOI layer. A thinned device channel region is formed in the exposed portion of the SOI layer and thereafter inner nitride spacers are formed on exposed walls of the fist nitride spacers. Next, a gate region is formed over the thinned device channel region and then the oxide layer is removed so as to expose thicker portions of the SOI layer than de device channel region.

摘要翻译： 提供了具有低源极和漏极电阻以及最小重叠电容的0.05微米通道长度的全耗尽SOI MOSFET器件及其制造方法。 根据本发明的方法，首先在SOI层顶部形成至少一个虚拟栅极区域。 虚拟栅极区域至少包括牺牲多晶硅区域和位于牺牲多晶硅区域的侧壁上的第一氮化物间隔物。 接下来，形成与伪栅极区的上表面共面的氧化物层，然后除去牺牲多晶硅区域，以露出SOI层的一部分。 在SOI层的暴露部分中形成一个变薄的器件沟道区，此后在第一氮化物间隔物的暴露的壁上形成内部氮化物间隔物。 接下来，在减薄的器件沟道区上形成栅极区，然后除去氧化物层，以便暴露出SOI层的比较器件沟道区更厚的部分。

公开(公告)号：US06841831B2

公开(公告)日：2005-01-11

申请号：US10461821

申请日：2003-06-13

申请人： Hussein I. Hanafi ,  Diane C. Boyd ,  Kevin K. Chan ,  Wesley Natzle ,  Leathen Shi

发明人： Hussein I. Hanafi ,  Diane C. Boyd ,  Kevin K. Chan ,  Wesley Natzle ,  Leathen Shi

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L29/76

CPC分类号： H01L29/78696 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/78612

摘要： A sub-0.05 μm channel length fully-depleted SOI MOSFET device having low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. The sub-0.05 μm channel length fully-depleted SOI MOSFET device includes an SOI structure which contains at least an SOI layer having a channel region of a first thickness and abutting source/drain regions of a second thickness present therein, wherein the second thickness is greater than the first thickness and the source/drain regions having a salicide layer present thereon. A gate region is present also atop the SOI layer.

摘要翻译： 提供了具有低源极和漏极电阻以及最小重叠电容的0.05微米通道长度的全耗尽SOI MOSFET器件及其制造方法。 子0.05通道长度全耗尽的SOI MOSFET器件包括SOI结构，其至少包含具有第一厚度的沟道区和邻接其中存在第二厚度的源极/漏极区的SOI层，其中第二厚度为 大于第一厚度，并且源/漏区具有存在于其上的自对准硅化物层。 栅极区也存在于SOI层的顶部。

公开(公告)号：US6143635A

公开(公告)日：2000-11-07

申请号：US374519

申请日：1999-08-16

申请人： Diane C. Boyd ,  Stuart M. Burns ,  Hussein I. Hanafi ,  Yuan Taur ,  William C. Wille

发明人： Diane C. Boyd ,  Stuart M. Burns ,  Hussein I. Hanafi ,  Yuan Taur ,  William C. Wille

IPC分类号： H01L21/76 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/08 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/66583 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823481 ,  H01L29/66537

摘要： Metal oxide semiconductor field effect transistor (MOSFET) including a drain region and a source region adjacent to a channel region. A gate oxide is situated on the channel region and a gate conductor with vertical side walls is placed on the gate oxide. The MOSFET further includes a threshold adjust implant region and/or punch through implant region being aligned with respect to the gate conductor and limited to an area underneath the gate conductor. Such a MOSFET can be made using the following method: forming a dielectric stack on a semiconductor structure; defining an etch window on the dielectric stack having the lateral size and shape of a gate hole to be formed; defining the gate hole in the dielectric stack by transferring the etch window into the dielectric stack using a reactive ion etching (RIE) process; implanting threshold adjust dopants and/or punch through dopants through the gate hole; depositing a gate conductor such that it fills the gate hole; removing the gate conductor covering portions of the semiconductor structure surrounding the gate hole; and removing at least part of the dielectric stack.

摘要翻译： 金属氧化物半导体场效应晶体管（MOSFET）包括漏极区域和与沟道区域相邻的源极区域。 栅极氧化物位于沟道区域上，并且具有垂直侧壁的栅极导体被放置在栅极氧化物上。 MOSFET还包括阈值调整注入区域和/或冲孔穿入注入区域，其相对于栅极导体对齐并且限制在栅极导体下方的区域。 这样的MOSFET可以使用以下方法制造：在半导体结构上形成介电堆叠; 在所述电介质堆叠上限定具有要形成的栅极孔的横向尺寸和形状的蚀刻窗口; 通过使用反应离子蚀刻（RIE）工艺将蚀刻窗口转移到电介质堆叠中来限定电介质叠层中的栅极孔; 植入阈值调节掺杂剂和/或穿过掺杂剂通过栅极孔; 沉积栅极导体，使其填充栅极孔; 去除覆盖围绕门孔的半导体结构的部分的栅极导体; 以及去除所述电介质叠层的至少一部分。

公开(公告)号：US6040214A

公开(公告)日：2000-03-21

申请号：US26261

申请日：1998-02-19

申请人： Diane C. Boyd ,  Stuart M. Burns ,  Hussein I. Hanafi ,  Yuan Taur ,  William C. Wille

发明人： Diane C. Boyd ,  Stuart M. Burns ,  Hussein I. Hanafi ,  Yuan Taur ,  William C. Wille

IPC分类号： H01L21/033 ,  H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L29/423 ,  H01L21/8242 ,  H01L21/20

CPC分类号： H01L29/66583 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/76224 ,  H01L29/42372

摘要： A method for the formation of field effect transistors (FETs), and more particularly metal oxide field effect transistors (MOSFETs), comprising the steps of: forming a dielectric stack on a semiconductor structure; defining an etch window on the dielectric stack; defining a gate hole in the dielectric stack by transferring the etch window into the dielectric stack using a reactive ion etching (RIE) process; depositing a side wall layer; removing the side wall layer from horizontal surfaces of the dielectric stack and gate hole such that side wall spacers remain which reduce the lateral size of the gate hole; depositing a gate conductor such that it fills the gate hole; removing the gate conductor covering the portions of the semiconductor structure surrounding the gate hole; removing at least part of the dielectric stack; and removing the side wall spacers.

摘要翻译： 一种形成场效应晶体管（FET）的方法，特别是金属氧化物场效应晶体管（MOSFET），包括以下步骤：在半导体结构上形成电介质叠层; 在电介质堆叠上限定蚀刻窗口; 通过使用反应离子蚀刻（RIE）工艺将蚀刻窗口转移到电介质堆叠中来在电介质叠层中限定栅极孔; 沉积侧壁层; 从介质堆叠和门孔的水平表面去除侧壁层，使得保留侧壁间隔物，这减小了闸门孔的横向尺寸; 沉积栅极导体，使其填充栅极孔; 去除覆盖围绕栅极孔的半导体结构的部分的栅极导体; 去除所述电介质叠层的至少一部分; 并移除侧壁间隔物。

公开(公告)号：US06461529B1

公开(公告)日：2002-10-08

申请号：US09299137

申请日：1999-04-26

申请人： Diane C. Boyd ,  Stuart M. Burns ,  Hussein I. Hanafi ,  Waldemar W. Kocon ,  William C. Wille ,  Richard Wise

发明人： Diane C. Boyd ,  Stuart M. Burns ,  Hussein I. Hanafi ,  Waldemar W. Kocon ,  William C. Wille ,  Richard Wise

IPC分类号： H01L213215

CPC分类号： H01L29/66583 ,  H01L21/31116 ,  H01L21/76224 ,  H01L21/823481

摘要： A process and etchant gas composition for anisotropically etching a trench in a silicon nitride layer of a multilayer structure. The etchant gas composition has an etchant gas including a polymerizing agent, a hydrogen source, an oxidant, and a noble gas diluent. The oxidant preferably includes a carbon-containing oxidant component and an oxidant-noble gas component. The fluorocarbon gas is selected from CF4, C2F6, and C3F8; the hydrogen source is selected from CHF3, CH2F2, CH3F, and H2; the oxidant is selected from CO, CO2, and O2; and the noble gas diluent is selected from He, Ar, and Ne. The constituents are added in amounts to achieve an etchant gas having a high nitride selectivity to silicon oxide and photoresist. A power source, such as an RF power source, is applied to the structure to control the directionality of the high density plasma formed by exciting the etchant gas. The power source that controls the directionality of the plasma is decoupled from the power source used to excite the etchant gas. The etchant gas can be used during a nitride etch step in a process for making a metal oxide semiconductor field effect transistor.

摘要翻译： 一种用于各向异性蚀刻多层结构的氮化硅层中的沟槽的工艺和蚀刻剂气体组合物。 蚀刻剂气体组合物具有包括聚合剂，氢源，氧化剂和惰性气体稀释剂的蚀刻剂气体。 氧化剂优选包括含碳氧化剂组分和氧化剂 - 惰性气体组分。 碳氟化合物气体选自CF4，C2F6和C3F8; 氢源选自CHF 3，CH 2 F 2，CH 3 F和H 2; 氧化剂选自CO，CO 2和O 2; 惰性气体稀释剂选自He，Ar和Ne。 添加成分以达到对氧化硅和光致抗蚀剂具有高氮化物选择性的蚀刻剂气体。 将诸如RF电源的电源施加到结构以控制通过激发蚀刻剂气体形成的高密度等离子体的方向性。 控制等离子体方向性的电源与用于激发蚀刻剂气体的电源脱耦。 在制造金属氧化物半导体场效应晶体管的工艺中的氮化物蚀刻步骤期间可以使用蚀刻剂气体。

公开(公告)号：US06593617B1

公开(公告)日：2003-07-15

申请号：US09026093

申请日：1998-02-19

申请人： Diane C. Boyd ,  Stuart M. Burns ,  Hussein I. Hanafi ,  Yuan Taur ,  William C. Wille

发明人： Diane C. Boyd ,  Stuart M. Burns ,  Hussein I. Hanafi ,  Yuan Taur ,  William C. Wille

IPC分类号： H01L2976

CPC分类号： H01L29/66583

摘要： Metal oxide semiconductor field effect transistor (MOSFET) comprising a drain region and source region which enclose a channel region. A thin gate oxide is situated on the channel region and a gate conductor with vertical side walls is located on this gate oxide. The interfaces between the source region and channel region and the drain region and channel region are abrupt. Such an FET can be made using the following method: forming a dielectric stack on a semiconductor structure which at least comprises a pad oxide layer; defining an etch window having the lateral size and shape of a gate pillar to be formed; defining a gate hole in the dielectric stack by transferring the etch window into the dielectric stack using a reactive ion etching (RIE) process; depositing a gate conductor such that it fills the gate hole; removing the gate conductor covering the portions of the dielectric stack surrounding the gate hole; removing at least part of the dielectric stack such that a gate pillar with vertical side walls is set free.

摘要翻译： 金属氧化物半导体场效应晶体管（MOSFET）包括漏极区域和封装沟道区域的源极区域。 栅极氧化物位于通道区域上，并且具有垂直侧壁的栅极导体位于该栅极氧化物上。 源极区域和沟道区域以及漏极区域和沟道区域之间的界面是突然的。可以使用以下方法制造FET：在至少包括衬垫氧化物层的半导体结构上形成电介质堆叠;限定蚀刻 窗口，其具有要形成的门柱的横向尺寸和形状;通过使用反应离子蚀刻（RIE）工艺将蚀刻窗口转移到电介质堆叠中来在电介质堆叠中限定栅极孔;沉积栅极导体，使得其填充 栅极孔;去除覆盖围绕栅极孔的电介质堆叠的部分的栅极导体;去除至少部分介电堆叠，使得具有垂直侧壁的门柱被释放。

公开(公告)号：US20080254622A1

公开(公告)日：2008-10-16

申请号：US12145113

申请日：2008-06-24

申请人： Ricky S. Amos ,  Diane C. Boyd ,  Cyril Cabral ,  Richard D. Kaplan ,  Jakub T. Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda C. Mocuta ,  Vijay Narayanan ,  An L. Steegen ,  Maheswaren Surendra

发明人： Ricky S. Amos ,  Diane C. Boyd ,  Cyril Cabral ,  Richard D. Kaplan ,  Jakub T. Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda C. Mocuta ,  Vijay Narayanan ,  An L. Steegen ,  Maheswaren Surendra

IPC分类号： H01L21/44

CPC分类号： H01L21/76897 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656

摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

摘要翻译： 本发明提供了一种互补金属氧化物半导体集成工艺，其中在栅极电介质顶部制造多个硅化金属栅极。 使用本发明的集成方案形成的每个硅化金属栅极与硅化物金属栅极的尺寸无关，具有相同的硅化物金属相和基本上相同的高度。 本发明还提供了形成具有硅化物触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。

公开(公告)号：US07002214B1

公开(公告)日：2006-02-21

申请号：US10710736

申请日：2004-07-30

申请人： Diane C. Boyd ,  Judson R. Holt ,  MeiKei Ieong ,  Renee T. Mo ,  Zhibin Ren ,  Ghavam G. Shahidi

发明人： Diane C. Boyd ,  Judson R. Holt ,  MeiKei Ieong ,  Renee T. Mo ,  Zhibin Ren ,  Ghavam G. Shahidi

IPC分类号： H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/76283 ,  H01L21/823892 ,  H01L21/84 ,  H01L29/66772 ,  H01L29/78609 ,  H01L29/78618 ,  H01L29/78696

摘要： A method of manufacture of a Super Steep Retrograde Well Field Effect Transistor device starts with an SOI layer formed on a substrate, e.g. a buried oxide layer. Thin the SOI layer to form an ultra-thin SOI layer. Form an isolation trench separating the SOI layer into N and P ground plane regions. Dope the N and P ground plane regions formed from the SOI layer with high levels of N-type and P-type dopant. Form semiconductor channel regions above the N and P ground plane regions. Form FET source and drain regions and gate electrode stacks above the channel regions. Optionally form a diffusion retarding layer between the SOI ground plane regions and the channel regions.

摘要翻译： 超陡逆行井场效应晶体管器件的制造方法从形成在衬底上的SOI层开始。 掩埋氧化层。 使SOI层变薄以形成超薄SOI层。 形成将SOI层分离成N和P接地平面区域的隔离沟槽。 用高水平的N型和P型掺杂剂掺杂由SOI层形成的N和P接地平面区域。 在N和P接地平面区域之上形成半导体沟道区。 在沟道区域上方形成FET源极和漏极区域以及栅极电极堆叠。 可选地，在SOI接地平面区域和沟道区域之间形成扩散延迟层。