公开(公告)号：US06938145B2

公开(公告)日：2005-08-30

申请号：US10309459

申请日：2002-12-04

申请人： Bruce A. Noyes ,  Russell W. Guenthner

发明人： Bruce A. Noyes ,  Russell W. Guenthner

IPC分类号： G06F12/10 ,  G06F12/00

CPC分类号： G06F12/1027

摘要： A computer system includes a central processing unit, an addressable main memory storing data pages and a page table, and an associative memory. The associative memory stores a plurality of entries in accordance with a low order virtual address component issued by the CPU's processor when access to a given page in main memory is sought. Each entry in the associative memory includes fields respectively holding: 1) a high order virtual address component; 2) a real page address; and 3) a multi-digit validity count. An incrementable multi-digit counter in the CPU stores a current validity count. When access to a data page is sought, a comparator receives: 1) the high order virtual address component of the data page; 2) the high order virtual address component read from the associative memory entry; 3) the multi-digit validity count read from the associative memory entry; and 4) the multi-digit current validity count in the counter. If there is a full match, a switch issues the real page address read from the associative memory entry. If there is not a match, the page table is consulted to obtain the real address of the requested page, and the associative memory is updated accordingly.

摘要翻译： 计算机系统包括中央处理单元，存储数据页和页表的可寻址主存储器和关联存储器。 关联存储器根据当CPU处理器发出的低阶虚拟地址组件访问主存储器中的给定页面时存储多个条目。 关联存储器中的每个条目包括分别保持：1）高阶虚拟地址分量的字段; 2）真实页面地址; 和3）多位数有效性计数。 CPU中可增量的多位计数器存储当前的有效性计数。 当寻求访问数据页时，比较器接收：1）数据页的高阶虚拟地址分量; 2）从关联存储器条目读取的高阶虚拟地址组件; 3）从关联存储器条目读取的多位数有效性计数; 和4）计数器中的多位数的当前有效性计数。 如果完全匹配，则交换机会发出从关联内存条目读取的真实页面地址。 如果没有匹配，则查询页表以获得所请求页面的真实地址，并且相关联的存储器被相应地更新。

公开(公告)号：US06199156B1

公开(公告)日：2001-03-06

申请号：US09212842

申请日：1998-12-16

申请人： Ronald W. Yoder ,  Lowell McCulley ,  Russell W. Guenthner

发明人： Ronald W. Yoder ,  Lowell McCulley ,  Russell W. Guenthner

IPC分类号： G06F1202

CPC分类号： G06F9/30076 ,  G06F9/3004 ,  G06F9/30105 ,  G06F9/30123 ,  G06F9/461

摘要： In a data processing system that includes a safe store buffer containing valid copies of all registers, processor transitions from a higher security routine to a lower security routine can be performed in fewer cycles by loading the safe store buffer from a safe store stack frame, then delaying loading registers either until actually utilized, or by a background process that loads registers utilizing unused memory cycles. A flag is used for each register that indicates whether the register contents are valid. This flag is cleared for each of the registers whenever such a state transition is made. Then, the flag is set for a register when it is referenced and made valid.

摘要翻译： 在包含包含所有寄存器的有效副本的安全存储缓冲器的数据处理系统中，可以通过从安全存储堆栈帧中加载安全存储缓冲区，以更少的周期执行从较高安全程序到较低安全程序的处理器转换，然后 延迟加载寄存器直到实际使用，或通过使用未使用的存储器周期加载寄存器的后台进程。 每个寄存器都使用一个标志，指示寄存器内容是否有效。 每当进行这种状态转换时，这个标志就被清除。 然后，当引用标志被设置为一个寄存器并被赋值。

公开(公告)号：US6014757A

公开(公告)日：2000-01-11

申请号：US994476

申请日：1997-12-19

申请人： Ronald W. Yoder ,  Russell W. Guenthner ,  Wayne R. Buzby

发明人： Ronald W. Yoder ,  Russell W. Guenthner ,  Wayne R. Buzby

IPC分类号： G06F9/38 ,  G06F11/14 ,  G06F11/00

CPC分类号： G06F11/1405 ,  G06F9/3863 ,  G06F11/1407

摘要： In order to gather, store temporarily and efficiently deliver safestore information in a CPU having data manipulation circuitry including a register bank, first and second serially oriented safestore buffers are employed. At suitable times during the processing of information, a copy of the instantaneous contents of the register bank is transferred into the first safestore buffer. After a brief delay, a copy of the first safestore buffer is transferred into the second safestore buffer. If a call for a domain change (which might include a process change or a fault) is sensed, a safestore frame is sent to cache, and the first safestore buffer is loaded from he second safestore buffer rather than from the register bank. Later, during a climb operation, if a restart of the interrupted process is undertaken and the restoration of the register bank is directed to be taken from the first safestore buffer, this source, rather than the safestore frame stored in cache, is employed to obtain a corresponding increase in the rate of restart. In one embodiment, the transfer of information between the register bank and the safestore buffers is carried out on a bit-by-bit basis to achieve additional flexibility of operation and also to conserve integrated circuit space.

摘要翻译： 为了收集，存储在具有包括寄存器组的数据操作电路的CPU中临时且有效地传送保险箱信息，采用第一和第二串行存取缓冲器。 在处理信息的适当时候，寄存器组的瞬时内容的副本被传送到第一个保险箱存储缓冲器。 经过短暂的延迟后，第一个safestore缓冲区的副本将被传输到第二个safestore缓冲区。 如果检测到域更改的呼叫（可能包括进程更改或故障），则将保险箱帧发送到缓存，并且第一个保险箱存储缓冲区从其第二个保险箱存储缓冲区加载，而不是从注册库中加载。 之后，在爬升操作期间，如果进行中断处理的重新启动，并且指示从第一个保险箱缓冲器取出寄存器组的恢复，则使用该源而不是存储在高速缓存中的保存存储帧来获得 相应地提高了重启速度。 在一个实施例中，在寄存器组和保险箱存储缓冲器之间的信息传输是在逐位的基础上进行的，以实现额外的操作灵活性并且还节省集成电路空间。

公开(公告)号：US4573116A

公开(公告)日：1986-02-25

申请号：US563350

申请日：1983-12-20

申请人： Richard H. Ong ,  Peter C. Economopoulos ,  Russell W. Guenthner

发明人： Richard H. Ong ,  Peter C. Economopoulos ,  Russell W. Guenthner

IPC分类号： G06F9/30 ,  G11C7/00 ,  G06F1/00

CPC分类号： G06F9/30141 ,  G11C7/00

摘要： An improved multiword data register array which features RAM technology to provide a greater memory capacity in a smaller space than a conventional register arrays. Whereas RAM technology does not ordinarily include the capability of simultaneously reading and writing, in accordance with the present invention, data may be written into the register on a first half cycle of a clock signal and read out of memory on the second half cycle of the same clock signal. If the writing and the reading of the data relate to the same address in the register array, the data may be read directly from the input circuit.

摘要翻译： 一种改进的多字数据寄存器阵列，其具有RAM技术，以在比常规寄存器阵列更小的空间中提供更大的存储容量。 而RAM技术通常不包括同时读取和写入的能力，根据本发明，可以在时钟信号的前半个周期将数据写入寄存器，并在存储器的第二个半周期读取存储器 相同的时钟信号。 如果数据的写入和读取与寄存器阵列中的相同地址相关，则可以直接从输入电路读取数据。

公开(公告)号：US4538238A

公开(公告)日：1985-08-27

申请号：US458794

申请日：1983-01-18

申请人： Joseph C. Circello ,  Russell W. Guenthner

发明人： Joseph C. Circello ,  Russell W. Guenthner

IPC分类号： G06F7/72 ,  G06F7/38

CPC分类号： G06F7/727

摘要： Method and apparatus for calculating the residue of a signed binary number of "n" bits with respect to a given check base m where m=2.sup.b -1. The bits of the binary number excluding the sign bit are partitioned into number segments, each of b bits starting with the least significant bit. If (n-1) is not an even multiple of b, higher order bit positions of the number segment containing the next most significant bit of the binary number are filled with logical zeros. A sign segment of b bits is formed. Both number and sign segments have boundaries. The bit position in the sign segment relative to a sign segment boundary which corresponds to the bit position of the sign bit "s" relative to the nearest boundary of a number segment is filled with a logical zero. All other bit positions of the sign segment are filled with the sign bit. The number and sign segments are applied to carry save adders to reduce the number segments and sign segment to a single sum segment and a single rotated carry segment. A rotated carry segment is a carry segment produced by a carry save adder, the most significant bit of which becomes the least significant bit of the rotated carry segment. The other bits of the carry segment and their significance are increased by one in the rotated carry segment. Carry segments produced by carry save adders of one level are converted to rotated carry segments before being applied to a carry save or full adder of a lower level. The single sum segment and single rotated carry segment produced by the lowest level carry save adder is applied to a one's complement adder. The b bit output of the one's complement adder is the residue of the signed binary number to the check base (2.sup.b -1).

摘要翻译： 用于计算相对于m = 2b-1的给定检验基数m的带符号二进制数“n”位的残差的方法和装置。 除符号位之外的二进制数的位被分割为数字段，每个b位以最低有效位开始。 如果（n-1）不是b的偶数倍，则包含二进制数的下一个最高有效位的数字段的高位位置被填充有逻辑0。 形成b位的符号段。 数字和符号段都有边界。 符号段相对于符号段边界相对于符号位“s”相对于数字段的最近边界的位位置的位位置用逻辑0填充。 符号段的所有其他位位置都用符号位填充。 数字和符号段被应用于携带保存加法器以减少数字段并将段标记到单个和段和单个旋转进位段。 旋转的进位段是由进位保存加法器产生的进位段，其最高有效位变为旋转进位段的最低有效位。 进位段的其他位及其重要性在旋转进位段增加1。 由一个级别的进位保存加法器产生的进位段在应用于较低级别的进位保存或全加器之前被转换为旋转的进位段。 由最低电平进位保存加法器产生的单个和段和单个旋转进位段应用于一个补码加法器。 补码加法器的b位输出是到校验基（2b-1）的带符号二进制数的残差。

公开(公告)号：US4359689A

公开(公告)日：1982-11-16

申请号：US111456

申请日：1980-01-11

申请人： Russell W. Guenthner

发明人： Russell W. Guenthner

IPC分类号： H03K5/15 ,  H03K5/156

CPC分类号： H03K5/15073

摘要： A clock pulse driver has applied to it a system clock pulse signal, or system clock and produces a first set of individually enabled clock pulse signals, the leading edges of the pulses of which substantially coincide with the leading edges of the pulses of the system clock, a second set and a third set of clock pulse signals, the trailing edges of the pulses of which substantially coincide with the leading edges of the pulses of the system clock. The width of the pulses of the three sets of output signals are controllable by first, second and third delay pulse signals. The clock pulse driver also produces delay signals the pulses of which have a predetermined relationship to the pulses of the system clock which delay signals can be used to control the widths of the first, second and third sets of clock signals produced by the driver circuits, and to control the delay or offset of the first, second and third sets of clock signals produced by the driver circuit.

摘要翻译： 时钟脉冲驱动器已经向其施加了系统时钟脉冲信号或系统时钟，并且产生第一组单独使能的时钟脉冲信号，其脉冲的前沿与系统时钟脉冲的前沿基本一致 ，第二组和第三组时钟脉冲信号，其脉冲的后沿与系统时钟的脉冲的前沿基本一致。 三组输出信号的脉冲宽度可由第一，第二和第三延迟脉冲信号控制。 时钟脉冲驱动器还产生延迟信号，其脉冲与系统时钟的脉冲具有预定的关系，延迟信号可用于控制由驱动器电路产生的第一，第二和第三组时钟信号的宽度， 并且控制由驱动器电路产生的第一，第二和第三组时钟信号的延迟或偏移。

公开(公告)号：US20140105452A1

公开(公告)日：2014-04-17

申请号：US13650413

申请日：2012-10-12

申请人： David Lowell Bowne ,  Shahrom Kiani ,  Carlos Macia ,  Russell W. Guenthner

发明人： David Lowell Bowne ,  Shahrom Kiani ,  Carlos Macia ,  Russell W. Guenthner

IPC分类号： G06K9/00

CPC分类号： G06K9/36 ,  G06K9/00973 ,  G06K2209/01

摘要： A scanning camera upgrade adaptor system provides backwards compatibility when an existing scanning camera subsystem is replaced or upgraded in automated sorting equipment with a newer camera having a different data format. The adaptor system allows sorting equipment such as mail sorting equipment to be upgraded or repaired with a new camera while providing compatibility and optional fallback to a previous mode of operation of the existing equipment. The upgrade system enables legacy equipment and newly added sorting/processing equipment to be utilized in conjunction, while reducing cost of upgrade and necessity for completely new equipment as desirable features are added.

摘要翻译： 当在具有不同数据格式的较新的相机的自动分选设备中更换或升级现有扫描相机子系统时，扫描相机升级适配器系统提供向后兼容性。 适配器系统允许使用新的相机对诸如邮件分类设备之类的分类设备进行升级或修理，同时提供与现有设备的先前操作模式的兼容性和可选的回退。 升级系统使传统设备和新添加的分拣/处理设备结合使用，同时降低升级成本，并增加全新设备的必要性。

公开(公告)号：US20100153735A1

公开(公告)日：2010-06-17

申请号：US12316771

申请日：2008-12-15

申请人： Russell W. Guenthner

发明人： Russell W. Guenthner

IPC分类号： H04K1/00 ,  H04L9/00

CPC分类号： G06F21/34 ,  H04L9/3226 ,  H04L2209/08

摘要： A secure method, apparatus or computer program incorporates a method for entering private information such as a user identifier, password or other secret code comprising at least one symbol or character. According to method in one illustrated embodiment, the user selects characters for input starting from presentation of an initial suggested character, moving under user control to presentation of a user's desired input character, and then followed by the selection by the user of that presented character as a character for data input. The method includes randomizing the timing of the display and/or reaction time to user input so that the number and timing of the key presses required to select any specific desired character for input is made unpredictable. This makes it difficult during entry of information to determine by covert means what specific information is being entered.

摘要翻译： 安全方法，装置或计算机程序包括用于输入诸如用户标识符，密码或包括至少一个符号或字符的其他密码的私人信息的方法。 根据一个所示实施例中的方法，用户从用户控制的显示开始，从显示初始建议字符开始输入用于输入用户的期望输入字符的用户的字符，然后由用户选择所呈现的字符作为 用于数据输入的字符。 该方法包括将显示和/或响应时间的定时随机化到用户输入，使得选择任何特定的所需字符以进行输入所需的按键的数量和定时变得不可预测。 这使得在信息输入期间难以通过隐蔽手段确定正在输入哪些具体信息。

公开(公告)号：US07689403B2

公开(公告)日：2010-03-30

申请号：US12148205

申请日：2008-04-17

申请人： Russell W. Guenthner ,  Sidney L Andress ,  John Heath

发明人： Russell W. Guenthner ,  Sidney L Andress ,  John Heath

IPC分类号： G06F9/455

CPC分类号： G06F9/30043 ,  G06F9/30101 ,  G06F9/30174

摘要： Two unique instructions for the instruction set of a target 36-bit machine which is emulated on a host 64-bit machine are provided in order to achieve visibility, to an emulated application program, of a “containing” word stored in the memory of the host machine. A “LOAD64” instruction loads the emulator memory location representing an emulated “Q” (supplementary accumulator) register with the “normal” 36-bits of the containing word. At the same time, the “upper” 28 bits of the 64-bit containing word is copied into the emulator memory location representing an emulated “A” (accumulator) register. Thus, the emulated 36-bit machine “sees” and can examine the 64-bit word in its entirety. A “Store64” instruction stores the emulated “Q” register contents into the lower 36-bits of the 64-bit containing word, and at the same time stores the lower 28 bits of the emulated “A” register contents into the upper 28 bits of the 64-bit containing word.

摘要翻译： 提供了用于在主机64位机器上仿真的目标36位机器的指令集的两个唯一指令，以便实现模拟应用程序对存储在存储器中的“包含”字的可见性 主机。 “LOAD64”指令将模拟器存储位置加载到包含字的“正常”36位的模拟“Q”（补充累加器）寄存器中。 同时，64位包含字的“上”28位被复制到表示仿真“A”（累加器）寄存器的仿真器存储单元中。 因此，仿真的36位机器“看到”并且可以检查64位字的整体。 “Store64”指令将模拟的“Q”寄存器内容存储到64位包含字的低36位，同时将模拟的“A”寄存器内容的低28位存储到高位28位 的64位包含字。

公开(公告)号：US5644761A

公开(公告)日：1997-07-01

申请号：US893871

申请日：1992-06-05

申请人： Ronald W. Yoder ,  Ronald E. Lange ,  William A. Shelly ,  Russell W. Guenthner ,  Richard L. Demers

发明人： Ronald W. Yoder ,  Ronald E. Lange ,  William A. Shelly ,  Russell W. Guenthner ,  Richard L. Demers

IPC分类号： G06F9/26 ,  G06F9/22

CPC分类号： G06F9/267

摘要： In order to efficiently undertake the micro-steps required to execute an extended instruction in a central processing unit, a main sequence controller and a separate basic operations controller having its own sequencer and the ability to run semi-autonomously are provided. Normally, the main sequence controller determines the operation of the basic operations controller, but, in the case of execution of, for example, a multi-word instruction requiring extended basic operations, the basic operations controller temporarily takes control over the main controller until the extended basic operations have been completed. The result is a relatively simple sequencer that supports tight micro-coded functions where many of the sequence decisions can be predetermined.

摘要翻译： 为了有效地执行在中央处理单元中执行扩展指令所需的微步骤，提供了具有其自己的定序器的主序列控制器和单独的基本操作控制器以及半自主运行的能力。 通常，主序列控制器确定基本操作控制器的操作，但是在执行例如需要扩展基本操作的多字指令的情况下，基本操作控制器暂时控制主控制器，直到 扩展基本操作已经完成。 结果是相对简单的定序器，其支持紧密的微编码功能，其中许多顺序决定可以被预先确定。