公开(公告)号：US20230342208A1

公开(公告)日：2023-10-26

申请号：US18218577

申请日：2023-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Oscar P. PINTO ,  William MARTIN

IPC: G06F9/50

CPC classification number: G06F9/5027

Abstract: An apparatus may include a device including at least one computational resource configured to perform a computational device function, and a circuit configured to access, based on an identifier, the computational device function, wherein the identifier may include protocol information for the computational device function. The protocol information may include information to pass a parameter. The information to pass the parameter may include information to pass a parameter to the computational device function. The information to pass the parameter may indicate a parameter passing technique. The parameter passing technique may include passing the parameter with a command. The parameter passing technique may include passing the parameter using a reference to the parameter. The identifier may include a first portion including at least a portion of the protocol information. The identifier may include a second portion including information to identify a functionality of the computational device function.

公开(公告)号：US20220357890A1

公开(公告)日：2022-11-10

申请号：US17705269

申请日：2022-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Oscar P. PINTO ,  William MARTIN

IPC: G06F3/06

Abstract: Provided are systems, methods, and apparatuses for managing functions for storage devices. The method can include: determining one or more functions associated with a first device and determining one or more corresponding function types for the functions; grouping the functions based on the function types using a group name; and providing the group name to a second device for use in connection with an associated application, wherein the storage device comprises a computational storage (CS) device.

公开(公告)号：US20220236902A1

公开(公告)日：2022-07-28

申请号：US17495810

申请日：2021-10-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Oscar P. PINTO ,  Ramdas P. KACHARE

IPC: G06F3/06 ,  G06F9/54

Abstract: Provided are systems, methods, and apparatuses for managing memory. The method can include: establishing a connection via an interface, between a host device and a storage device; and transferring data, via the interface, between first memory associated with the host device and second memory associated with the storage device by performing a data operation on the second memory by an application executed by the host, where the storage device includes a processing element that accelerates the data operation by performing at least one offload function on the data operation.

公开(公告)号：US20210263762A1

公开(公告)日：2021-08-26

申请号：US17006773

申请日：2020-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ramdas P. KACHARE ,  Oscar P. PINTO ,  Yang seok KI

IPC: G06F9/455 ,  G06F3/06 ,  G06F12/0862

Abstract: A storage device is disclosed. The storage device may include at least one controller for a virtual machine (VM) that is on a source host. Storage in the storage device may store data for the VM. A second storage may store a storage state for the VM. A storage device controller may process at least one read request received from the controller for the VM using the first storage and at least one write request received from the controller for the VM using the first storage. A VM migration state monitor and capture module may assist in the migration of the VM from the source host to a destination host.

公开(公告)号：US20190310957A1

公开(公告)日：2019-10-10

申请号：US16260087

申请日：2019-01-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sompong Paul OLARIG ,  Fred WORLEY ,  Oscar P. PINTO

IPC: G06F13/40 ,  G06F13/16 ,  G06F13/42

Abstract: A topology is disclosed. The topology may include at least one Non-Volatile Memory Express (NVMe) Solid State Drive (SSD), a Field Programmable Gate Array (FPGA) to implement one or more functions supporting the NVMe SSD, such as data acceleration, data deduplication, data integrity, data encryption, and data compression, and a Peripheral Component Interconnect Express (PCIe) switch. The PCIe switch may communicate with both the FPGA and the NVMe SSD.