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    NOVEL SSD ARCHITECTURE FOR FPGA BASED ACCELERATION
    3.
    发明申请
    NOVEL SSD ARCHITECTURE FOR FPGA BASED ACCELERATION 审中-公开

    公开(公告)号：US20190272242A1

    公开(公告)日：2019-09-05

    申请号：US16124183

    申请日：2018-09-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ramdas P. KACHARE ,  Fred WORLEY

    IPC: G06F13/16 ,  G06F13/42

    Abstract: A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream port enables communication with the processor; a downstream port enables communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction. A downstream filter associated with the downstream port may intercept an acceleration instruction associated with a downstream Filter Address Range (FAR) received from the storage device and deliver the acceleration instruction to the APM-F, the acceleration instruction being. The processor, the acceleration module, and the storage device may communicate via a Peripheral Component Interconnect Exchange (PCIe) bus. The acceleration module may support performing the acceleration instruction on the application data on the storage device for the application program without loading the application data into the memory.

    NOVEL SSD ARCHITECTURE FOR FPGA BASED ACCELERATION
    4.
    发明申请
    NOVEL SSD ARCHITECTURE FOR FPGA BASED ACCELERATION 审中-公开

    公开(公告)号：US20190272240A1

    公开(公告)日：2019-09-05

    申请号：US16122865

    申请日：2018-09-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ramdas P. KACHARE ,  Fred WORLEY ,  Harry ROGERS ,  Wentao WU ,  Nagarajan SUBRAMANIYAN

    IPC: G06F13/16 ,  G06F13/42 ,  G06F13/40

    Abstract: A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream interface enables communication with the processor; a downstream interface enables communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction. The processor, the acceleration module, and the storage device may communicate via a Peripheral Component Interconnect Exchange (PCIe) bus. The acceleration module may support performing the acceleration instruction on the application data on the storage device for the application program without loading the application data into the memory.

    MODULAR SYSTEM ARCHITECTURE FOR SUPPORTING MULTIPLE SOLID-STATE DRIVES
    5.
    发明申请
    MODULAR SYSTEM ARCHITECTURE FOR SUPPORTING MULTIPLE SOLID-STATE DRIVES 有权

    公开(公告)号：US20250103533A1

    公开(公告)日：2025-03-27

    申请号：US18973890

    申请日：2024-12-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sompong Paul OLARIG ,  Fred WORLEY

    IPC: G06F13/40 ,  G06F13/16

    Abstract: A rack-mountable data storage system includes: a chassis including one or more switchboards; a midplane interfacing with the one or more switchboards; and one or more data storage devices removably coupled to the midplane using a connector. At least one data storage device of the one or more data storage devices include a logic device to interface with the midplane. The logic device provides a device-specific interface of a corresponding data storage device with the midplane. The at least one data storage device is configured using the logic device according to a first protocol based on a signal on a pin of the connector, and the at least one data storage device is reconfigurable according to a second protocol based on a change of the signal on the pin of the connector using the logic device.

    TWO-HEADED SWITCH INCLUDING A DRIVE BAY FOR FABRIC-ATTACHED DEVICES
    8.
    发明申请
    TWO-HEADED SWITCH INCLUDING A DRIVE BAY FOR FABRIC-ATTACHED DEVICES 审中-公开

    公开(公告)号：US20180048592A1

    公开(公告)日：2018-02-15

    申请号：US15280842

    申请日：2016-09-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Fred WORLEY ,  Sompong Paul OLARIG

    IPC: H04L12/935 ,  H04L12/931

    CPC classification number: H04L49/30 ,  H04L49/351 ,  H04L49/356

    Abstract: A switch includes a chassis, a drive bay including a plurality of downlink switch ports that are configured to be connected to a plurality of storage devices, a plurality of uplink switch ports, and an embedded circuit for providing signal switching between the plurality of uplink switch ports and the plurality of downlink switch ports. The drive bay is disposed on a first side of the chassis, and the plurality of uplink switch ports are disposed on a second side of the chassis that is opposite to the first side of the chassis. The plurality of downlink switch ports is embedded in the drive bay.

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