公开(公告)号：US20210376642A1

公开(公告)日：2021-12-02

申请号：US17085117

申请日：2020-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beomwoo GU ,  Kangho BYUN ,  Hyunseok SHIN ,  Sungku YEO ,  Youngho RYU ,  Chongmin LEE

IPC: H02J7/00 ,  H02J50/12 ,  H02J50/80 ,  H02J7/02

Abstract: According to an embodiment, an electronic device may include a battery, a resonance circuit, a rectifier, a DC/DC converter, a charger, a switch, an overvoltage protection circuit configured to perform an overvoltage protection operation or to stop the overvoltage protection operation based on the voltage at the output terminal of the rectifier, a control circuit, and a communication circuit, and the control circuit may be configured to: based on a periodic repetition of a performance of the overvoltage protection operation and a stop of the overvoltage protection while the switch is in an off state, identify a first period during which the overvoltage protection operation is stopped, based on the first period, identify an expected voltage at an output terminal of the rectifier, to be expected, wherein the expected voltage is a voltage if the switch is in an on state, based on the expected voltage, identify whether an occurrence of an overvoltage is expected if the switch is in the on state, and control the communication circuit to transmit a communication signal including information about whether the occurrence of the overvoltage is expected.

公开(公告)号：US20190222205A1

公开(公告)日：2019-07-18

申请号：US16248159

申请日：2019-01-15

Applicant: Samsung Electronics Co., Ltd. ,  Korea Advanced Institute of Science and Technology

Inventor： Sungku YEO ,  Gwanghyeon JEONG ,  Songcheol HONG ,  Jaeseok PARK ,  Seunghun WANG ,  Youngho RYU ,  Junhan LIM

IPC: H03K5/00 ,  H03H11/32 ,  H03M1/66 ,  H03K17/687

CPC classification number: H03K5/00 ,  H02J50/10 ,  H03H11/32 ,  H03K17/687 ,  H03K2005/00286 ,  H03M1/66

Abstract: A vector sum circuit and a phase controller including the vector sum circuit are provided. The vector sum circuit includes an amplifier configured to amplify an input orthogonal signal by using a first metal oxide semiconductor field effect transistor (MOSFET), and a self body-biasing circuit comprising a resistor. The self body-biasing circuit is configured to connect a drain and a body of the first MOSFET to reduce a voltage connected to the body as a current at the drain increases.