公开(公告)号：US20190222205A1

公开(公告)日：2019-07-18

申请号：US16248159

申请日：2019-01-15

申请人： Samsung Electronics Co., Ltd. ,  Korea Advanced Institute of Science and Technology

发明人： Sungku YEO ,  Gwanghyeon JEONG ,  Songcheol HONG ,  Jaeseok PARK ,  Seunghun WANG ,  Youngho RYU ,  Junhan LIM

IPC分类号： H03K5/00 ,  H03H11/32 ,  H03M1/66 ,  H03K17/687

CPC分类号： H03K5/00 ,  H02J50/10 ,  H03H11/32 ,  H03K17/687 ,  H03K2005/00286 ,  H03M1/66

摘要： A vector sum circuit and a phase controller including the vector sum circuit are provided. The vector sum circuit includes an amplifier configured to amplify an input orthogonal signal by using a first metal oxide semiconductor field effect transistor (MOSFET), and a self body-biasing circuit comprising a resistor. The self body-biasing circuit is configured to connect a drain and a body of the first MOSFET to reduce a voltage connected to the body as a current at the drain increases.

公开(公告)号：US20190204886A1

公开(公告)日：2019-07-04

申请号：US16299019

申请日：2019-03-11

申请人： Intel Corporation

发明人： Michael Zelikson ,  Vjekoslav Svilan ,  Norbert Unger ,  Shai Rotem

IPC分类号： G06F1/26 ,  G06F1/3287 ,  G06F1/3234 ,  H03K17/687

CPC分类号： G06F1/26 ,  G06F1/3243 ,  G06F1/3287 ,  H03K17/687 ,  Y02D10/152 ,  Y02D10/171

摘要： Methods and systems to adjust a resistance between a supply grid and a power-gated grid during an active state of a power-gated circuitry in response to load changes in the circuitry to maintain a relatively consistent IR droop. Subsets of power gates (PGs) may be selectively enabled and disabled based on changes in a load factor, such as a voltage, which may be monitored at a gated power distribution grid and/or proximate to a transistor gate within the power-gated circuitry. The adjusting may be performed to minimize a difference between the monitored voltage and a reference, such as with successive approximation or CMS software. PG subsets may be distributed within one or more layers of an integrated circuit (IC) die and may be selectively enabled/disabled based on location. PGs may be embedded within lower layers of an integrated circuit (IC) die, such as within metal layers of the IC die.

公开(公告)号：US20190201958A1

公开(公告)日：2019-07-04

申请号：US16330198

申请日：2017-09-12

申请人： TRUMPF Maschinen Austria GmbH & Co. KG.

发明人： Thomas BINDER ,  Philipp CAHA ,  Markus PITTRICH

IPC分类号： B21D5/00 ,  B21D5/02

CPC分类号： B21D5/004 ,  B21D5/0209 ,  B21D5/0254 ,  G05B2219/49304 ,  H03K17/687

摘要： The invention relates to a bending tool (1) comprising a tool body (2) having an upper (3) and an opposite lower end region (4), wherein an attachment extension (5) is configured in the upper end region (3), and a working tip (6) is configured in the lower end region (4). A tool identification marker (11) is disposed in the tool body (2), and a communication interface (9) is disposed in the attachment extension (5) on at least one side surface (8) and not projecting beyond it, which interface is connected with the tool identification marker (11) by way of a connection line (10). An electronics unit (12) is disposed in the tool body (2). A voltage supply contact (14) that is electrically insulated relative to the tool body (2) is is disposed on the attachment extension (5), which contact is connected with a voltage supply module (15) of the electronics unit (12). Furthermore, a change-over switch (16) is disposed in the connection line (10), wherein in a first switching position, the tool identification marker (11) is connected with the communication interface (9), and in a second switching position of the change-over switch (16), the electronics unit (12) is connected with the communication interface (9).

公开(公告)号：US20190181858A1

公开(公告)日：2019-06-13

申请号：US16273851

申请日：2019-02-12

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Olivier Trescases ,  Johan Tjeerd Strydom ,  Rajarshi Mukhopadhyay

IPC分类号： H03K17/687 ,  H03K17/042 ,  H03K5/08 ,  H01L29/16

CPC分类号： H03K17/687 ,  H01L29/1608 ,  H03K5/08 ,  H03K17/04206 ,  H03K17/0822

摘要： Methods and circuitry for driving a device through drive cycles wherein each drive cycle has a plurality of drive stages are disclosed. An example of the circuitry includes an output for coupling the circuitry to the device and a plurality of drive slices coupled in parallel to the output. Control circuitry selectively activates individual drive slices in the plurality of drive slices during each stage of a drive cycle.

公开(公告)号：US20190181852A1

公开(公告)日：2019-06-13

申请号：US15915718

申请日：2018-03-08

申请人： Delta Electronics (Thailand) Public Company Limited

发明人： Cheevanantachai Phichej

IPC分类号： H03K17/16 ,  H03K17/687 ,  H03K5/24

CPC分类号： H03K17/161 ,  H03K5/24 ,  H03K17/687 ,  H03K2217/0054

摘要： An ORing circuit is provided. The ORing circuit includes an input port, an output port, an ORing FET, a comparing circuit, a first transistor and a second transistor. The ORing FET is connected between the input port and the output port and comprises a source connected with the input port, a gate and a drain connected with the output port. The comparing circuit is connected with the input port and the gate. The first transistor comprises a first terminal, a second terminal and a third terminal. The first terminal is connected with the input port and the source, and the third terminal is connected with the gate. The second transistor comprises a fourth terminal, a fifth terminal and a sixth terminal. The fourth terminal is connected with the output port and the drain, and the sixth terminal is connected with the second terminal of the first transistor.

公开(公告)号：US20190165785A1

公开(公告)日：2019-05-30

申请号：US16202012

申请日：2018-11-27

申请人： LAPIS SEMICONDUCTOR CO., LTD.

发明人： KATSUYOSHI YAGI

IPC分类号： H03K19/003 ,  H03K19/00 ,  H03K17/687

CPC分类号： H03K19/00315 ,  H03K17/687 ,  H03K19/0013

摘要： An input/output circuit including: a first transistor that, based on an input signal and an enable signal input to an enable terminal that switches a validity and invalidity of an output, drives a load connected between an output terminal and an external power supply; a first switch provided between the input terminal and a control terminal of the first transistor, and including a first switching terminal that switches between connecting or blocking the input signal; and a switch control section that controls the first switching terminal based on the enable signal, wherein, when a logic of the enable signal has transitioned, the switch control section controls the first switching terminal to cause the first switch to be in a connecting state for a predetermined period, to input the input signal to the control terminal of the first transistor, and to suppress a current flowing to the load.

公开(公告)号：US20190157393A1

公开(公告)日：2019-05-23

申请号：US16097592

申请日：2016-06-08

申请人： Intel Corporation

发明人： Jeanette M. Roberts ,  Ravi Pillarisetty ,  David J. Michalak ,  Zachary R. Yoscovits ,  James S. Clarke

IPC分类号： H01L29/12 ,  H01L29/778 ,  H01L29/49 ,  H01L29/423 ,  H03K17/687 ,  H01L29/66 ,  H01L21/321 ,  H01L21/28 ,  H01L29/165

CPC分类号： H01L29/127 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/28088 ,  H01L21/3212 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/423 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66431 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66977 ,  H01L29/7613 ,  H01L29/778 ,  H01L29/7781 ,  H01L29/7782 ,  H03K17/687

摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; and one or more gates disposed on the fin. In some such embodiments, the one or more gates may include first, second, and third gates. Spacers may be disposed on the sides of the first and second gates, such that a first spacer is disposed on a side of the first gate proximate to the second gate, and a second spacer, physically separate from the first spacer, is disposed on a side of the second gate proximate to the first gate. The third gate may be disposed on the fin between the first and second gates and extend between the first and second spacers.

公开(公告)号：US20190140601A1

公开(公告)日：2019-05-09

申请号：US16161500

申请日：2018-10-16

申请人： Realtek Semiconductor Corp.

发明人： Chao-Huang WU ,  Yi-Shao CHANG ,  Han-Chang KANG ,  Ka-Un CHAN

IPC分类号： H03F1/26 ,  H04B1/10 ,  H03G5/16

CPC分类号： H03F1/26 ,  H03F3/45179 ,  H03G5/16 ,  H03G5/28 ,  H03K17/687 ,  H04B1/10

摘要： A dual-mode signal amplifying circuit includes: a first and a second input terminals for receiving differential input signals; two output terminals for providing differential output signals; a first through a third current sources; a first switch positioned between the first current source and a first node, and controlled by the first input terminal; a second switch positioned between the first current source and a second node, and controlled by the second input terminal; a third switch positioned between the first node and a fixed-voltage terminal, and controlled by a third node; a fourth switch positioned between the second node and a fixed-voltage terminal, and controlled by the third node; a fifth switch positioned between the second current source and a fixed-voltage terminal, and controlled by the first node; and a sixth switch positioned between the third current source and a fixed-voltage terminal, and controlled by the second node.

公开(公告)号：US20190103867A1

公开(公告)日：2019-04-04

申请号：US16086935

申请日：2017-03-21

申请人： AUTONETWORKS TECHNOLOGIES, LTD. ,  SUMITOMO WIRING SYSTEMS, LTD. ,  SUMITOMO ELECTRIC INDUSTRIES, LTD.

发明人： Yuuki SUGISAWA

IPC分类号： H03K17/687 ,  H03K17/693 ,  H03K17/30 ,  H02J7/00

CPC分类号： H03K17/6872 ,  H02J7/00 ,  H02J7/0063 ,  H03K17/302 ,  H03K17/687 ,  H03K17/693

摘要： A power supply control device that includes a controller configured to switch on and off a first semiconductor switch and a plurality of second semiconductor switches whose current input terminals are connected to a current output terminal of the first semiconductor switch, the controller being configured to control supply of power via the plurality of second semiconductor switches by switching; a first parasitic diode connected between a current input terminal and the current output terminal of the first semiconductor switch; and a plurality of second parasitic diodes that are respectively connected between the current input terminals and current output terminals of the plurality of second semiconductor switches.

公开(公告)号：US20180375512A1

公开(公告)日：2018-12-27

申请号：US15731768

申请日：2015-09-17

申请人： CSMC TECHNOLOGIES FAB2 CO., LTD

发明人： Yun GAO

IPC分类号： H03K17/22 ,  G06F1/24 ,  G05F3/24 ,  H03K17/687

CPC分类号： H03K17/223 ,  G05F3/24 ,  G06F1/24 ,  H03K17/22 ,  H03K17/687

摘要： A power on reset circuit, comprising: a threshold level control circuit (120) configured to set threshold level values of power on reset and power off reset; a capacitor charge and discharge circuit (130) configured to output a power on reset signal according to the threshold level values set by the threshold level control circuit; and a current bias circuit (110) configured to provide a reference current not varying with a power supply to the threshold level control circuit (120) and the capacitor charge and discharge circuit (130), comprising: a first reference current output terminal connected to the threshold level control circuit (120); a second reference current output terminal connected to the capacitor charge and discharge circuit (130); and a third reference current output terminal connected to the capacitor charge and discharge circuit (130).