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公开(公告)号:US11024741B2
公开(公告)日:2021-06-01
申请号:US16747870
申请日:2020-01-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Seungmin Song , Bongseok Suh , Junggil Yang , Soojin Jeong
IPC: H01L29/78 , H01L29/06 , H01L29/08 , H01L29/423
Abstract: An integrated circuit includes a fin active region protruding from a substrate, a plurality of semiconductor patterns on an upper surface of the fin active region, a gate electrode that surrounds the plurality of semiconductor patterns and includes a main gate part on an uppermost one of the plurality of semiconductor patterns and sub gate parts between the plurality of semiconductor patterns, a spacer structure on a sidewall of the main gate part, and a source/drain region at a side of the gate electrode. The source/drain region is connected to the plurality of semiconductor patterns and contacts a bottom surface of the spacer structure. A top portion of the uppermost semiconductor pattern has a first width. A bottom portion of the uppermost semiconductor pattern has a second width smaller than the first width.
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公开(公告)号:US09711506B2
公开(公告)日:2017-07-18
申请号:US15249518
申请日:2016-08-29
Applicant: Samsung Electronics Co. Ltd.
Inventor: Junggil Yang , Sangsu Kim , TaeYong Kwon , Sung Gi Hur
IPC: H01L21/8238 , H01L27/092 , H01L21/306 , H01L29/10 , H01L29/423
CPC classification number: H01L27/0924 , H01L21/30604 , H01L21/30612 , H01L21/823807 , H01L21/823821 , H01L27/0922 , H01L29/1054 , H01L29/42392
Abstract: A method of fabricating a semiconductor device includes preparing a substrate including a first region and a second region, sequentially forming a first semiconductor layer and a second semiconductor layer on the first and second regions, patterning the first and second semiconductor layers to form a lower semiconductor pattern and an upper semiconductor pattern on each of the first and second regions, selectively removing the lower semiconductor pattern on the second region to form a gap region, and forming gate electrodes at the first and second regions, respectively.
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