公开(公告)号：US10153214B2

公开(公告)日：2018-12-11

申请号：US15386843

申请日：2016-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se Jung Park ,  Ju-Hyun Kim ,  Hoyoung Kim ,  Boun Yoon ,  TaeYong Kwon ,  Sangkyun Kim ,  Sanghyun Park

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/84 ,  H01L21/3105 ,  H01L21/306 ,  H01L27/092

Abstract: A patterning method for fabricating a semiconductor device includes forming, for example sequentially forming, a lower buffer layer, a first channel semiconductor layer, and a capping insulating layer on a substrate, forming an opening to penetrate the capping insulating layer and the first channel semiconductor layer and expose a portion of the lower buffer layer, forming a second channel semiconductor layer to fill the opening and include a first portion protruding above the capping insulating layer, performing a first CMP process to remove at least a portion of the first portion, removing the capping insulating layer, and performing a second CMP process to remove at least a portion of a second portion of the second channel semiconductor layer protruding above the first channel semiconductor layer.

公开(公告)号：US11114447B2

公开(公告)日：2021-09-07

申请号：US16793912

申请日：2020-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghun Lee ,  TaeYong Kwon ,  Dongwon Kim

IPC: H01L27/11 ,  H01L27/11582 ,  H01L27/092 ,  H01L29/417

Abstract: An SRAM device includes first, second and third transistors, which are used as a pass gate transistor, a pull-down transistor, and a pull-up transistor, respectively. A channel region of each transistor may include a plurality of semiconductor sheets that are vertically stacked on a substrate. The semiconductor sheets used as the channel regions of the first and second transistors may have a width greater than the semiconductor sheets used as channel regions of the third transistor.

公开(公告)号：US10177150B2

公开(公告)日：2019-01-08

申请号：US15615643

申请日：2017-06-06

Applicant: Samsung Electronics Co. Ltd.

Inventor： Junggil Yang ,  Sangsu Kim ,  TaeYong Kwon ,  Sung Gi Hur

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/306 ,  H01L29/423 ,  H01L29/10

Abstract: A method of fabricating a semiconductor device includes preparing a substrate including a first region and a second region, sequentially forming a first semiconductor layer and a second semiconductor layer on the first and second regions, patterning the first and second semiconductor layers to form a lower semiconductor pattern and an upper semiconductor pattern on each of the first and second regions, selectively removing the lower semiconductor pattern on the second region to form a gap region, and forming gate electrodes at the first and second regions, respectively.

公开(公告)号：US20160268394A1

公开(公告)日：2016-09-15

申请号：US15165931

申请日：2016-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Gi Hur ,  TaeYong Kwon ,  Sangsu Kim ,  Jungdal Choi

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L29/66553 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7849

Abstract: A semiconductor device includes a substrate having a first region and a second region, a first MOS transistor including a first fin structure and a first gate electrode in the first region, the first fin structure having a first buffer pattern, a second buffer pattern, and a first channel pattern which are sequentially stacked on the substrate, and a second MOS transistor including a second fin structure and a second gate electrode in the second region, the second fin structure having a third buffer pattern and a second channel pattern which are sequentially stacked on the substrate. Related fabrication methods are also discussed.

公开(公告)号：US10741564B2

公开(公告)日：2020-08-11

申请号：US15255652

申请日：2016-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghun Lee ,  TaeYong Kwon ,  Dongwon Kim

IPC: H01L27/11 ,  H01L27/11582 ,  H01L27/092 ,  H01L29/417

Abstract: An SRAM device includes first, second and third transistors, which are used as a pass gate transistor, a pull-down transistor, and a pull-up transistor, respectively. A channel region of each transistor may include a plurality of semiconductor sheets that are vertically stacked on a substrate. The semiconductor sheets used as the channel regions of the first and second transistors may have a width greater than the semiconductor sheets used as channel regions of the third transistor.

公开(公告)号：US09595610B2

公开(公告)日：2017-03-14

申请号：US14723673

申请日：2015-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： TaeYong Kwon ,  Shigenobu Maeda ,  David Seo ,  Jae-Hwan Lee

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7849 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/785

Abstract: A MOSFET may be formed with a strain-inducing mismatch of lattice constants that improves carrier mobility. In exemplary embodiments a MOSFET includes a strain-inducing lattice constant mismatch that is not undermined by a recessing step. In some embodiments a source/drain pattern is grown without a recessing step, thereby avoiding problems associated with a recessing step. Alternatively, a recessing process may be performed in a way that does not expose top surfaces of a strain-relaxed buffer layer. A MOSFET device layer, such as a strain-relaxed buffer layer or a device isolation layer, is unaffected by a recessing step and, as a result, strain may be applied to a channel region without jeopardizing subsequent formation steps.

Abstract translation: 可以形成MOSFET，其具有改善载流子迁移率的晶格常数的应变诱导失配。 在示例性实施例中，MOSFET包括不会被凹陷步骤破坏的应变诱导晶格常数失配。 在一些实施例中，源/漏图案在没有凹陷步骤的情况下生长，从而避免与凹陷步骤相关的问题。 或者，可以以不暴露应变松弛缓冲层的顶表面的方式执行凹陷处理。 诸如应变松弛缓冲层或器件隔离层的MOSFET器件层不受凹陷步骤的影响，结果可能将应变施加到沟道区而不会影响随后的形成步骤。

公开(公告)号：US09502531B2

公开(公告)日：2016-11-22

申请号：US15165931

申请日：2016-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Gi Hur ,  TaeYong Kwon ,  Sangsu Kim ,  Jungdal Choi

IPC: H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/66 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L29/66553 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7849

Abstract: A semiconductor device includes a substrate having a first region and a second region, a first MOS transistor including a first fin structure and a first gate electrode in the first region, the first fin structure having a first buffer pattern, a second buffer pattern, and a first channel pattern which are sequentially stacked on the substrate, and a second MOS transistor including a second fin structure and a second gate electrode in the second region, the second fin structure having a third buffer pattern and a second channel pattern which are sequentially stacked on the substrate. Related fabrication methods are also discussed.

Abstract translation: 半导体器件包括具有第一区域和第二区域的衬底，第一区域中包括第一鳍结构和第一栅电极的第一MOS晶体管，第一鳍结构具有第一缓冲图案，第二缓冲图案和 依次层叠在基板上的第一沟道图案和在第二区域中包括第二鳍结构和第二栅电极的第二MOS晶体管，第二鳍结构具有顺序堆叠的第三缓冲图案和第二沟道图案 在基板上。 还讨论了相关的制造方法。

公开(公告)号：US09466601B2

公开(公告)日：2016-10-11

申请号：US14274861

申请日：2014-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junggil Yang ,  Sangsu Kim ,  TaeYong Kwon ,  Sung Gi Hur

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L29/1054 ,  H01L29/42392

Abstract: A semiconductor device includes a substrate including first and second regions, a first transistor provided on the first region to include a first channel region protruding from the substrate, and a second transistor provided on the second region to include a second channel region and a gate electrode extending between the substrate and the second channel region. The first channel region may include a lower semiconductor pattern containing a different material from the second channel region and an upper semiconductor pattern containing the same material as the second channel region.

Abstract translation: 半导体器件包括包括第一和第二区域的衬底，第一晶体管，设置在第一区域上，以包括从衬底突出的第一沟道区域;以及第二晶体管，设置在第二区域上以包括第二沟道区域和栅电极 在衬底和第二沟道区之间延伸。 第一沟道区可以包括含有与第二沟道区不同的材料的下半导体图案和包含与第二沟道区相同的材料的上半导体图案。

公开(公告)号：US11271110B2

公开(公告)日：2022-03-08

申请号：US16693439

申请日：2019-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Jong Lee ,  Sanghyuk Hong ,  TaeYong Kwon ,  Sunjung Kim ,  Cheol Kim

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66 ,  H01L21/8238

Abstract: Semiconductor devices and methods of fabricating the same are provided. The methods of fabricating the semiconductor devices may include providing a substrate including an active pattern protruding from the substrate, forming a first liner layer and a field isolating pattern on the substrate to cover a lower portion of the active pattern, forming a second liner layer on an upper portion of the active pattern and the field isolation pattern, and forming a dummy gate on the second liner layer.

公开(公告)号：US10410886B2

公开(公告)日：2019-09-10

申请号：US15602599

申请日：2017-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： TaeYong Kwon ,  Sangjin Kim ,  Donghoon Hwang ,  Sebeom Oh ,  Yunkyeong Jang

IPC: H01L21/56 ,  H01L21/311 ,  H01L21/8234 ,  H01L23/544 ,  H01L21/308

Abstract: Methods of fabricating a semiconductor device are provided. The methods may include forming a lower mold layer on a substrate that includes first and second regions, forming first and second intermediate mold patterns on the first and second regions, respectively, forming first spacers on sidewalls of the first and second intermediate mold patterns, etching the lower mold layer to form first and second lower mold patterns on the first and second regions, respectively, and etching the substrate to form active patterns and dummy patterns on the first and second regions, respectively. A first distance between a pair of the first intermediate mold patterns may be greater than a second distance between a pair of the second intermediate mold patterns, and the second lower mold patterns may include at least one first merged pattern, whose width is substantially equal to the second distance.