公开(公告)号：US20100259986A1

公开(公告)日：2010-10-14

申请号：US12802910

申请日：2010-06-16

申请人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

发明人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

IPC分类号： G11C16/04

CPC分类号： G11C16/0466 ,  G11C16/0475 ,  H01L27/115

摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

公开(公告)号：US20100259981A1

公开(公告)日：2010-10-14

申请号：US12802888

申请日：2010-06-16

申请人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

发明人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

IPC分类号： G11C16/04

CPC分类号： G11C16/0466 ,  G11C16/0475 ,  H01L27/115

摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

公开(公告)号：US20050111279A1

公开(公告)日：2005-05-26

申请号：US10756568

申请日：2004-01-13

申请人： Seiki Ogura ,  Yutaka Hayashi ,  Tomoko Ogura

发明人： Seiki Ogura ,  Yutaka Hayashi ,  Tomoko Ogura

IPC分类号： G11C11/56 ,  G11C16/04 ,  H01L21/8246 ,  H01L27/115 ,  G11C11/34

CPC分类号： H01L27/11568 ,  G11C11/5671 ,  G11C16/0475 ,  H01L27/115

摘要： A fast low voltage ballistic program, ultra-short channel, ultra-high density, dual-bit multi-level flash memory is described with a two or three polysilicon split gate side wall process. The structure and operation of this invention is enabled by a twin MONOS cell structure having an ultra-short control gate channel of less than 40 nm, with ballistic injection which provides high electron injection efficiency and very fast program at low program voltages of 3˜5V. The cell structure is realized by (i) placing side wall control gates over a composite of Oxide-Nitride-Oxide (ONO) on both sides of the word gate, and (ii) forming the control gates and bit diffusion by self-alignment and sharing the control gates and bit diffusions between memory cells for high density. Key elements used in this process are: 1) Disposable side wall process to fabricate the ultra short channel and the side wall control gate with or without a step structure, and 2) Self-aligned definition of the control gate over the storage nitride and the bit line diffusion, which also runs in the same direction as the control gate. The features of fast program, low voltage, ultra-high density, dual-bit, multi-level MONOS NVRAM of the present invention include: 1) Electron memory storage in nitride regions within an ONO layer underlying the control gates, 2) high density dual-bit cell in which there are two nitride memory storage elements per cell, 3) high density dual-bit cell can store multi-levels in each of the nitride regions, 4) low current program controlled by the word gate and control gate, 5) fast, low voltage program by ballistic injection utilizing the controllable ultra-short channel MONOS, and 6) side wall control poly gates to program and read multi-levels while masking out memory storage state effects of the unselected adjacent nitride regions and memory cells. The ballistic MONOS memory cell is arranged in the following array: each memory cell contains two nitride regions for one word gate, and ½ a source diffusion and ½ a bit diffusion. Control gates can be defined separately or shared together over the same diffusion. Diffusions are shared between cells and run in parallel to the side wall control gates, and perpendicular to the word line.

公开(公告)号：US06807105B2

公开(公告)日：2004-10-19

申请号：US10371519

申请日：2003-02-20

申请人： Seiki Ogura ,  Tomoko Ogura ,  Nori Ogura

发明人： Seiki Ogura ,  Tomoko Ogura ,  Nori Ogura

IPC分类号： G11C1604

CPC分类号： G11C16/3459 ,  G11C16/0475 ,  G11C16/12 ,  G11C16/3454

摘要： In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.

摘要翻译： 在本发明中，描述了用于程序和程序验证的新方法。 存储单元的阈值电压向上移动，然后以最小的位线和控制栅线的充电和放电进行测量。 位线控制栅极线电容也用于减少所需的电压基准数量。 通过使用耦合到源扩散的负载装置来减少编程电流。 结果是增加了程序带宽，具有较低的高电压电荷泵电流消耗。

公开(公告)号：US06628547B2

公开(公告)日：2003-09-30

申请号：US10371839

申请日：2003-02-20

申请人： Seiki Ogura ,  Tomoko Ogura ,  Nori Ogura

发明人： Seiki Ogura ,  Tomoko Ogura ,  Nori Ogura

IPC分类号： G11C1604

CPC分类号： G11C16/3459 ,  G11C16/0475 ,  G11C16/12 ,  G11C16/3454

摘要： In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.

公开(公告)号：US6038169A

公开(公告)日：2000-03-14

申请号：US270596

申请日：1999-03-18

申请人： Seiki Ogura ,  Tomoko Ogura

发明人： Seiki Ogura ,  Tomoko Ogura

IPC分类号： G11C11/56 ,  G11C16/28 ,  G11C16/04

CPC分类号： G11C11/5642 ,  G11C11/5621 ,  G11C16/28 ,  G11C2211/5634

摘要： In this invention a reference circuit is disclosed that produces a reference current to be used in determining the value of data in a flash memory cell. The memory cell current is compared to the reference current in a sense amplifier. A reference circuit that generates the reference current is connect to each bit line of the flash memory and uses bit lines that are not activated when a particular cell is being read to connect the reference current to the sense amplifiers. The use of a reference current allows multi-bit cells to be read by using a variation on the reference circuit that has a plurality of reference transistors creating a plurality of reference currents.. Verification of the programmed and erase states of a flash memory cell can be determined using different values of the reference current that are easily set in the reference circuit by changing a reference voltage.

摘要翻译： 在本发明中，公开了一种参考电路，其产生用于确定闪存单元中的数据值的参考电流。 将存储单元电流与读出放大器中的参考电流进行比较。 产生参考电流的参考电路连接到闪存的每个位线，并且使用当读取特定单元以将参考电流连接到读出放大器时未被激活的位线。 使用参考电流允许通过使用具有多个参考晶体管的参考电路上的变化来读取多位单元，该参考电路产生多个参考电流。闪存单元的编程和擦除状态的验证可以 可以通过改变参考电压来容易地在参考电路中设置的参考电流的不同值来确定。

公开(公告)号：US08139410B2

公开(公告)日：2012-03-20

申请号：US12802910

申请日：2010-06-16

申请人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

发明人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

IPC分类号： G11C16/04

CPC分类号： G11C16/0466 ,  G11C16/0475 ,  H01L27/115

摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

公开(公告)号：US08023326B2

公开(公告)日：2011-09-20

申请号：US12802894

申请日：2010-06-16

申请人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

发明人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

IPC分类号： G11C16/04

CPC分类号： G11C16/0466 ,  G11C16/0475 ,  H01L27/115

摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

摘要翻译： 非易失性陷阱电荷存储单元选择在可编程逻辑应用中使用的逻辑互连晶体管，例如FPGA。 非挥发性捕获电荷元件是位于控制栅极下方并位于半导体衬底表面上的氧化物之上的绝缘体。 优选实施例是集成器件，其包括夹在两个非易失性陷阱电荷存储部分之间的字门部分，其中该集成器件连接在高偏压，低偏压和输出之间。 输出由连接到字栅极下方的通道的扩散形成。 两个存储部分的编程状态确定高偏压或低偏压是否耦合到连接到输出扩散的逻辑互连晶体管。

公开(公告)号：US07742336B2

公开(公告)日：2010-06-22

申请号：US11982172

申请日：2007-11-01

申请人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

发明人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

IPC分类号： G11C16/04

CPC分类号： G11C16/0466 ,  G11C16/0475 ,  H01L27/115

摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

公开(公告)号：US06856545B2

公开(公告)日：2005-02-15

申请号：US10371520

申请日：2003-02-20

申请人： Seiki Ogura ,  Tomoko Ogura ,  Nori Ogura

发明人： Seiki Ogura ,  Tomoko Ogura ,  Nori Ogura

IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/12 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00 ,  G11C11/34 ,  G11C7/01

CPC分类号： G11C16/3459 ,  G11C16/0475 ,  G11C16/12 ,  G11C16/3454

摘要： In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.

摘要翻译： 在本发明中，描述了用于程序和程序验证的新方法。 存储单元的阈值电压向上移动，然后以最小的位线和控制栅线的充电和放电进行测量。 位线控制栅极线电容也用于减少所需的电压基准数量。 通过使用耦合到源扩散的负载装置来减少编程电流。 结果是增加了程序带宽，降低了高电压电荷泵的电流消耗。