公开(公告)号：US20100261324A1

公开(公告)日：2010-10-14

申请号：US12802894

申请日：2010-06-16

申请人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

发明人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

IPC分类号： H01L21/336

CPC分类号： G11C16/0466 ,  G11C16/0475 ,  H01L27/115

摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

摘要翻译： 非易失性陷阱电荷存储单元选择在可编程逻辑应用中使用的逻辑互连晶体管，例如FPGA。 非挥发性捕获电荷元件是位于控制栅极下方并位于半导体衬底表面上的氧化物之上的绝缘体。 优选实施例是集成器件，其包括夹在两个非易失性陷阱电荷存储部分之间的字门部分，其中该集成器件连接在高偏压，低偏压和输出之间。 输出由连接到字栅极下方的通道的扩散形成。 两个存储部分的编程状态确定高偏压或低偏压是否耦合到连接到输出扩散的逻辑互连晶体管。

公开(公告)号：US20100259985A1

公开(公告)日：2010-10-14

申请号：US12802895

申请日：2010-06-16

申请人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

发明人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

IPC分类号： G11C16/04

CPC分类号： G11C16/0466 ,  G11C16/0475 ,  H01L27/115

摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

公开(公告)号：US20080101117A1

公开(公告)日：2008-05-01

申请号：US11982172

申请日：2007-11-01

申请人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

发明人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

IPC分类号： G11C16/04 ,  H01L21/336

CPC分类号： G11C16/0466 ,  G11C16/0475 ,  H01L27/115

摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

摘要翻译： 非易失性陷阱电荷存储单元选择在可编程逻辑应用中使用的逻辑互连晶体管，例如FPGA。 非挥发性捕获电荷元件是位于控制栅极下方并位于半导体衬底表面上的氧化物之上的绝缘体。 优选实施例是集成器件，其包括夹在两个非易失性陷阱电荷存储部分之间的字门部分，其中该集成器件连接在高偏压，低偏压和输出之间。 输出由连接到字栅极下方的通道的扩散形成。 两个存储部分的编程状态确定高偏压或低偏压是否耦合到连接到输出扩散的逻辑互连晶体管。

公开(公告)号：US07149126B2

公开(公告)日：2006-12-12

申请号：US10756568

申请日：2004-01-13

申请人： Seiki Ogura ,  Yutaka Hayashi ,  Tomoko Ogura

发明人： Seiki Ogura ,  Yutaka Hayashi ,  Tomoko Ogura

IPC分类号： G11C16/04

CPC分类号： H01L27/11568 ,  G11C11/5671 ,  G11C16/0475 ,  H01L27/115

摘要： A fast low voltage ballistic program, ultra-short channel, ultra-high density, dual-bit multi-level flash memory is described. The structure and operation of this invention is enabled by a twin MONOS cell structure having an ultra-short control gate channel of less than 40 nm, with ballistic injection which provides high electron injection efficiency and very fast program at low program voltages of 3˜5V. The ballistic MONOS memory cell is arranged in the following array: each memory cell contains two nitride regions for one word gate, and ½ a source diffusion and ½ a bit diffusion. Control gates can be defined separately or shared together over the same diffusion. Diffusions are shared between cells and run in parallel to the side wall control gates, and perpendicular to the word line.

摘要翻译： 描述了一种快速低电压弹道程序，超短通道，超高密度双位多级闪存。 本发明的结构和操作通过具有小于40nm的超短控制栅极通道的双重MONOS单元结构实现，具有提供高电子注入效率的弹道注入和在3〜5V的低编程电压下非常快速的程序 。 弹道MONOS存储单元被布置在以下阵列中：每个存储单元包含用于一个字门的两个氮化物区域，以及1/2扩散源和1/2位扩散。 控制门可以单独定义，也可以通过相同的扩散共享。 扩散在单元之间共享并且平行于侧壁控制栅极并垂直于字线。

公开(公告)号：US06636439B1

公开(公告)日：2003-10-21

申请号：US10371840

申请日：2003-02-20

申请人： Seiki Ogura ,  Tomoko Ogura ,  Nori Ogura

发明人： Seiki Ogura ,  Tomoko Ogura ,  Nori Ogura

IPC分类号： G11C1604

CPC分类号： G11C16/3459 ,  G11C16/0475 ,  G11C16/12 ,  G11C16/3454

摘要： In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.

公开(公告)号：US06549463B2

公开(公告)日：2003-04-15

申请号：US10016916

申请日：2001-12-14

申请人： Seiki Ogura ,  Tomoko Ogura ,  Nori Ogura

发明人： Seiki Ogura ,  Tomoko Ogura ,  Nori Ogura

IPC分类号： G11C1604

CPC分类号： G11C16/3459 ,  G11C16/0475 ,  G11C16/12 ,  G11C16/3454

摘要： In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.

公开(公告)号：US06542412B2

公开(公告)日：2003-04-01

申请号：US10058484

申请日：2002-01-28

申请人： Seiki Ogura ,  Tomoko Ogura

发明人： Seiki Ogura ,  Tomoko Ogura

IPC分类号： G11C1604

CPC分类号： H01L27/11521 ,  G11C11/5621 ,  G11C16/0425 ,  G11C16/0475 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11524

摘要： A fast program, ultra-high density, dual-bit, multi-level flash memory process, which can be applied to a ballistic step split gate side wall transistor, or to a ballistic planar split gate side wall transistor, which enables low voltage requirement on the floating gate during erase is described. Two side wall floating gates are paired with a single word line select gate, and word lines are arranged to be perpendicular to both the bit lines and control gate lines. Adjacent memory cells on the same word line share bitline diffusion as well as a third poly control gate. Control gates allow erase access to the individual floating gate.

摘要翻译： 一种快速程序，超高密度，双位，多级闪存过程，可应用于弹道分割栅侧壁晶体管，或可应用于弹道平面分裂栅侧壁晶体管，可实现低电压要求 在擦除时在浮动栅上进行描述。 两个侧壁浮动栅极与单个字线选择栅极配对，并且字线被布置成垂直于位线和控制栅极线。 相同字线上的相邻存储单元共享位线扩散以及第三个多路控制门。 控制门允许擦除访问各个浮动门。

公开(公告)号：US20100046302A1

公开(公告)日：2010-02-25

申请号：US12583743

申请日：2009-08-25

申请人： Nori Ogura ,  Tomoko Ogura ,  Seiki Ogura

发明人： Nori Ogura ,  Tomoko Ogura ,  Seiki Ogura

IPC分类号： G11C16/06 ,  G11C16/04 ,  G11C7/02

CPC分类号： G11C16/06 ,  G11C7/04 ,  G11C7/06 ,  G11C7/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0466 ,  G11C16/10 ,  G11C2211/5647

摘要： Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits.

摘要翻译： 描述了存储器单元的互补配对的方法。 这些方法包括互补对中的两个物理存储器单元，每个擦除块的互补对参考单元，以及存储多个数据位的物理互补对。

公开(公告)号：US20070030745A1

公开(公告)日：2007-02-08

申请号：US11500115

申请日：2006-08-07

申请人： Tomoko Ogura ,  Nori Ogura ,  Seiki Ogura ,  Yoshitaka Baba

发明人： Tomoko Ogura ,  Nori Ogura ,  Seiki Ogura ,  Yoshitaka Baba

IPC分类号： G11C7/02 ,  G11C16/06 ,  G11C11/34

CPC分类号： G11C7/14 ,  G11C16/0475 ,  G11C16/28 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459

摘要： A reference circuit is described for creating a reference signal using a twin MONOS memory cell. A first portion of the twin MONOS memory cell connects to a charged and floating bit line a current source formed in a second portion of the twin MONOS cell that discharges the charged bit line to form a reference signal for a sense amplifier. The sense amplifier compares the reference signal to a signal from a selected memory cell upon which memory operations are being performed comprising read, erase verify and program verify.

摘要翻译： 描述了使用双MONOS存储单元创建参考信号的参考电路。 双MONOS存储器单元的第一部分连接到充电和浮置位线，形成在双MONOS单元的第二部分中的电流源，其对充电的位线进行放电以形成用于读出放大器的参考信号。 读出放大器将参考信号与来自执行存储器操作的所选存储器单元的信号进行比较，包括读取，擦除验证和程序验证。

公开(公告)号：US07006378B1

公开(公告)日：2006-02-28

申请号：US10742987

申请日：2003-12-22

申请人： Tomoya Saito ,  Tomoko Ogura ,  Kimihiro Satoh ,  Seiki Ogura

发明人： Tomoya Saito ,  Tomoko Ogura ,  Kimihiro Satoh ,  Seiki Ogura

IPC分类号： G11C16/04

CPC分类号： G11C16/0475

摘要： A nonvolatile memory device is achieved. The device comprises a string of MONOS cells connected drain to source. Each MONOS cell comprises a wordline gate overlying a channel region in a substrate. First and second control gates each overlying a channel region in the substrate. The wordline gate channel region is laterally between first and second control gate channel regions. An ONO layer is vertically between the control gates and the substrate. The nitride layer of the ONO layer forms a charge storage site for each control gate. First and second doped regions, forming a source and a drain, are in the substrate. The wordline gate channel region and the control gate channel regions are between the first doped region and the second doped region. First and second transistors connect the topmost MONOS cell to a first bit line and the bottom most MONOS cell to a second bit line.

摘要翻译： 实现非易失性存储器件。 该装置包括一串连接到源极的MONOS电池。 每个MONOS单元包括覆盖衬底中的沟道区的字线门。 第一和第二控制栅极，每个覆盖衬底中的沟道区域。 字线栅极沟道区域横向在第一和第二控制栅极沟道区域之间。 ONO层在控制栅极和衬底之间垂直。 ONO层的氮化物层形成每个控制栅极的电荷存储位置。 在衬底中形成源极和漏极的第一和第二掺杂区域。 字线栅极沟道区和控制栅沟道区在第一掺杂区和第二掺杂区之间。 第一和第二晶体管将最上面的MONOS单元连接到第一位线，将最底部的MONOS单元连接到第二位线。