公开(公告)号：US20230411479A1

公开(公告)日：2023-12-21

申请号：US17841687

申请日：2022-06-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Lung-Kun Chu ,  Jia-Ni Yu ,  Chun-Fu Lu ,  Chung-Wei Hsu ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L21/8234 ,  H01L29/78

CPC分类号： H01L29/42392 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/6656 ,  H01L29/7851 ,  H01L21/823468 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/66795 ,  H01L21/823431

摘要： A semiconductor device and a manufacturing method thereof are provided. The method includes the following steps. A fin structure extending along a first direction and having a lower fin structure and an upper fin structure disposed over the lower fin structure is formed, the upper fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. A sacrificial gate structure extending along a second direction perpendicular to the first direction is formed over the upper fin structure. Gate spacers are formed on the sacrificial gate structure. A portion of the sacrificial gate structure is removed to expose the gate spacers. Portions of the exposed gate spacers are removed to form a first gate trench with a first dimension along the first direction. The rest of the sacrificial gate structure is removed to form a second gate trench with a second dimension along the first direction under the first gate trench, wherein the first dimension is greater than the second dimension. A gate dielectric and a first work function metal layer sequentially covering the first and second gate trenches are formed, wherein a first portion of the first work function metal layer merge in the second gate trench, and a second portion of the first work function metal layer is located on sidewalls of the first gate trench. The second portion of the first work function metal layer is removed to expose the gate dielectric located on sidewalls of the first gate trench while remaining the first portion of the first work function metal layer. A second work function metal layer is formed over the first portion of the first work function metal layer to fill the first gate trench.

公开(公告)号：US20230378302A1

公开(公告)日：2023-11-23

申请号：US18361665

申请日：2023-07-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Wei Hsu ,  Kuo-Cheng Chiang ,  Mao-Lin Huang ,  Lung-Kun Chu ,  Jia-Ni Yu ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC分类号： H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/786

CPC分类号： H01L29/42392 ,  H01L21/823828 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/78696

摘要： A structure has stacks of semiconductor layers over a substrate and adjacent a dielectric feature. A gate dielectric is formed wrapping around each layer and the dielectric feature. A first layer of first gate electrode material is deposited over the gate dielectric and the dielectric feature. The first layer on the dielectric feature is recessed to a first height below a top surface of the dielectric feature. A second layer of the first gate electrode material is deposited over the first layer. The first gate electrode material in a first region of the substrate is removed to expose a portion of the gate dielectric in the first region, while the first gate electrode material in a second region of the substrate is preserved. A second gate electrode material is deposited over the exposed portion of the gate dielectric and over a remaining portion of the first gate electrode material.

公开(公告)号：US11450664B2

公开(公告)日：2022-09-20

申请号：US17105108

申请日：2020-11-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Mao-Lin Huang ,  Lung-Kun Chu ,  Chung-Wei Hsu ,  Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

摘要： A semiconductor device structure is provided. The device includes first semiconductor layers and second semiconductor layers disposed below and aligned with the first semiconductor layers. Each first semiconductor layer is surrounded by a first and fourth intermixed layers. The first intermixed layer is disposed between the first semiconductor layer and the fourth intermixed layer and includes a first and second materials. The fourth intermixed layer includes a third and fourth materials. Each second semiconductor layer is surrounded by a second and third intermixed layers. The second intermixed layer is disposed between the second semiconductor layer and the third intermixed layer and includes the first and a fifth material. The third intermixed layer includes the third and a sixth material. The second and fourth material are a dipole material having a first polarity, and the fifth and sixth material are a dipole material having a second polarity opposite the first polarity.

公开(公告)号：US20220173096A1

公开(公告)日：2022-06-02

申请号：US17676403

申请日：2022-02-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Mao-Lin Huang ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Jia-Ni Yu ,  Lung-Kun Chu ,  Chung-Wei Hsu

IPC分类号： H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/786

摘要： In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first transistor having a first conductivity type arranged over a substrate. The first transistor includes a first gate electrode layer having a first work function and extending from a first source/drain region to a second source/drain region, and a first channel structure embedded in the first gate electrode layer and extending from the first source/drain region to the second source/drain region. A second transistor having the first conductivity type is arranged laterally beside the first transistor. The second transistor includes a second gate electrode layer having a second work function that is different than the first work function and extending from a third source/drain region to a fourth source/drain region. A second channel structure is embedded in the second gate electrode layer and extends from the third source/drain region to the fourth source/drain region.