公开(公告)号：US12183799B2

公开(公告)日：2024-12-31

申请号：US18447870

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jung-Chien Cheng ,  Kuo-Cheng Chiang ,  Shi Ning Ju ,  Guan-Lin Chen ,  Jia-Chuan You ,  Chia-Hao Chang ,  Chih-Hao Wang ,  Kuan-Lun Cheng

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes a first channel member over a first backside dielectric feature, a first gate structure engaging the first channel member, a second channel member over a second backside dielectric feature, a second gate structure engaging the second channel member, and a first isolation feature includes a first portion laterally between the first and second backside dielectric features and a second portion laterally between the first and second gate structures. The first isolation feature is in physical contact with the first and second gate structures.

公开(公告)号：US20240371877A1

公开(公告)日：2024-11-07

申请号：US18775982

申请日：2024-07-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jung-Chien Cheng ,  Kuo-Cheng Chiang ,  Shi Ning Ju ,  Guan-Lin Chen ,  Chih-Hao Wang ,  Kuan-Lun Cheng

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure includes first channel members vertically stacked, second channel members vertically stacked, a first source/drain feature abutting the first channel members, a second source/drain feature abutting the second channel members, a first gate structure engaging the first channel members, a second gate structure engaging the second channel members, a first metal interconnect layer disposed at a frontside of the semiconductor device, and a second metal interconnect layer disposed at a backside of the semiconductor device. The first and second gate structures are stacked vertically between the first and second metal interconnect layers. The exemplary semiconductor structure also includes an isolation structure stacked vertically between the first and second metal interconnect layers. The isolation structure includes an air gap stacked laterally between the first and second gate structures.

公开(公告)号：US20240355625A1

公开(公告)日：2024-10-24

申请号：US18758948

申请日：2024-06-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Wei Hsu ,  Kuo-Cheng Chiang ,  Mao-Lin Huang ,  Lung-Kun Chu ,  Jia-Ni Yu ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/033 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/28185 ,  H01L21/02603 ,  H01L21/0332 ,  H01L21/28088 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78696

Abstract: A structure includes first nanostructures vertically spaced one from another over a substrate in a core region of the semiconductor structure, a first interfacial layer wrapping around each of the first nanostructures, a first high-k dielectric layer over the first interfacial layer and wrapping around each of the first nanostructures, second nanostructures vertically spaced one from another over the substrate in an I/O region of the semiconductor structure, a second interfacial layer wrapping around each of the second nanostructures, a second high-k dielectric layer over the second interfacial layer and wrapping around each of the second nanostructures. The first nanostructures have a first vertical pitch, the second nanostructures have a second vertical pitch substantially equal to the first vertical pitch, the first nanostructures have a first vertical spacing, the second nanostructures have a second vertical spacing greater than the first vertical spacing by about 4 Å to about 20 Å.

公开(公告)号：US20240347640A1

公开(公告)日：2024-10-17

申请号：US18757165

申请日：2024-06-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Yi Chuang ,  Hou-Yu Chen ,  Kuan-Lun Cheng

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/02293 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823487 ,  H01L29/6681 ,  H01L29/66818

Abstract: A semiconductor device according to the present disclosure includes a first transistor and a second transistor disposed over the first transistor. The first transistor includes a plurality of channel members vertically stacked over one another, and a first source/drain feature adjoining the plurality of channel members. The second transistor includes a fin structure, and a second source/drain feature adjoining the fin structure. The semiconductor device further includes a conductive feature electrically connecting the first source/drain feature and the second source/drain feature.

公开(公告)号：US20240321643A1

公开(公告)日：2024-09-26

申请号：US18737166

申请日：2024-06-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Cheng Chiang ,  Shi Ning Ju ,  Guan-Lin Chen ,  Jung-Chien Cheng ,  Chih-Hao Wang ,  Kuan-Lun Cheng

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor structure includes a first stack of active channel layers and a second stack of active channel layers disposed over a semiconductor substrate, where the second stacking include a dummy channel layer and the first stack is free of any dummy channel layer, a gate structure engaged with the first stack and the second stack, and first S/D features disposed adjacent to the first stack and second S/D features disposed adjacent to the second stack, where the second S/D features overlap with the dummy channel layer.

公开(公告)号：US20240312994A1

公开(公告)日：2024-09-19

申请号：US18672218

申请日：2024-05-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jung-Chien Cheng ,  Chih-Hao Wang ,  Guan-Lin Chen ,  Shi Ning Ju ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78621 ,  H01L29/78696

Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a first base portion and a second base portion, an isolation feature sandwiched between the first base portion and the second base portion, a center dielectric fin over the isolation feature, a first anti-punch-through (APT) feature over the first base portion, a second APT feature over the second base portion, a first stack of channel members over the first APT feature, and a second stack of channel members over the second APT feature. The center dielectric fin is sandwiched between the first stack of channel members and the second stack of channel members as well as between the first APT feature and the second APT feature.

公开(公告)号：US12068370B2

公开(公告)日：2024-08-20

申请号：US18141077

申请日：2023-04-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chi-Yi Chuang ,  Cheng-Ting Chung ,  Hou-Yu Chen ,  Kuan-Lun Cheng

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B10/00

CPC classification number: H01L29/0665 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78618 ,  H10B10/125

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes first and second source/drain epitaxial features, a first gate electrode layer disposed between the first and second source/drain epitaxial features, third and fourth source/drain epitaxial features, a second gate electrode layer disposed between the third and fourth source/drain epitaxial features, fifth and sixth source/drain epitaxial features disposed over the first and second source/drain epitaxial features, and a third gate electrode layer disposed between the fifth and sixth source/drain epitaxial features. The third gate electrode layer is electrically connected to the second source/drain epitaxial feature. The structure further includes a seventh source/drain epitaxial feature disposed over the third source/drain epitaxial feature and an eighth source/drain epitaxial feature disposed over the fourth source/drain epitaxial feature. The second gate electrode layer is disposed between the seventh and eighth source/drain epitaxial features.

公开(公告)号：US11996334B2

公开(公告)日：2024-05-28

申请号：US18069052

申请日：2022-12-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Wei Hsu ,  Kuo-Cheng Chiang ,  Mao-Lin Huang ,  Lung-Kun Chu ,  Jia-Ni Yu ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L21/823857 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/0669 ,  H01L29/42392

Abstract: A method includes providing a first channel layer and a second channel layer over a substrate; forming a first patterned hard mask covering the first channel layer and exposing the second channel layer; selectively depositing a cladding layer on the second channel layer and not on the first patterned hard mask; performing a first thermal drive-in process; removing the first patterned hard mask; after removing the first patterned hard mask, forming an interfacial dielectric layer on the cladding layer and the first channel layer; and forming a high-k dielectric layer on the interfacial dielectric layer.

公开(公告)号：US11990374B2

公开(公告)日：2024-05-21

申请号：US18084051

申请日：2022-12-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kuan-Ting Pan ,  Kuo-Cheng Chiang ,  Shi Ning Ju ,  Yi-Ruei Jhan ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/823468 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78696

Abstract: Embodiments of the present disclosure provide a method of forming sidewall spacers by filling a trench between a hybrid fin and a semiconductor fin structure. The sidewall spacer includes two fin sidewall spacer portions connected by a gate sidewall spacer portion. The fin sidewall spacer portion has a substantially uniform profile to provide uniform protection for vertically stacked channel layers and eliminate any gaps and leaks between inner spacers and sidewall spacers.

公开(公告)号：US11923361B2

公开(公告)日：2024-03-05

申请号：US17857740

申请日：2022-07-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shi-Ning Ju ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0886 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66787 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor fin over a substrate and multiple semiconductor nanostructures suspended over the semiconductor fin. The semiconductor device structure also includes a gate stack extending across the semiconductor fin, and the gate stack wraps around each of the semiconductor nanostructures. The semiconductor device structure further includes a first epitaxial structure and a second epitaxial structure sandwiching the semiconductor nanostructures. In addition, the semiconductor device structure includes an isolation structure between the semiconductor fin and the gate stack. The isolation structure extends exceeding opposite sidewalls of the first epitaxial structure.