公开(公告)号：US20240322013A1

公开(公告)日：2024-09-26

申请号：US18188964

申请日：2023-03-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun-Fu LU ,  Chih-Hao Wang ,  Wang-Chun Huang ,  Kuo-Cheng Chiang ,  Mao-Lin Huang ,  Jia-Ni Yu ,  Lung-Kun Chu ,  Chung-Wei Hsu

IPC分类号： H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L29/66666 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/516 ,  H01L29/66553 ,  H01L29/6684 ,  H01L29/7827 ,  H01L29/78391

摘要： A method for manufacturing a semiconductor structure includes forming first and second channel layers over a substrate, forming first source/drain features over the first and second channel layers, forming a gate dielectric layer wrapping around the first and second channel layers, forming a first work function layer wrapping around the gate dielectric layer, forming a hard mask layer wrapping around the first work function layer, removing portions of the hard mask layer and the first work function layer, removing the hard mask layer and the first work function layer wrapping around the second channel layer, removing the hard mask layer wrapping around the first channel layer, forming a second work function layer wrapping around the first work function layer and the second channel layer, forming a metal material between the second work function layer, and forming second source/drain features under the first and second channel layers.

公开(公告)号：US12040191B2

公开(公告)日：2024-07-16

申请号：US18069315

申请日：2022-12-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Wei Hsu ,  Kuo-Cheng Chiang ,  Mao-Lin Huang ,  Lung-Kun Chu ,  Jia-Ni Yu ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/033 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L21/28185 ,  H01L21/02603 ,  H01L21/0332 ,  H01L21/28088 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78696

摘要： A structure includes first nanostructures vertically spaced one from another over a substrate in a core region of the semiconductor structure, a first interfacial layer wrapping around each of the first nanostructures, a first high-k dielectric layer over the first interfacial layer and wrapping around each of the first nanostructures, second nanostructures vertically spaced one from another over the substrate in an I/O region of the semiconductor structure, a second interfacial layer wrapping around each of the second nanostructures, a second high-k dielectric layer over the second interfacial layer and wrapping around each of the second nanostructures. The first nanostructures have a first vertical pitch, the second nanostructures have a second vertical pitch substantially equal to the first vertical pitch, the first nanostructures have a first vertical spacing, the second nanostructures have a second vertical spacing greater than the first vertical spacing by about 4 Å to about 20 Å.

公开(公告)号：US11637195B2

公开(公告)日：2023-04-25

申请号：US17087131

申请日：2020-11-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Lung-Kun Chu ,  Mao-Lin Huang ,  Chung-Wei Hsu ,  Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

摘要： A method of fabricating a device includes providing a fin extending from a substrate, the fin having a plurality of semiconductor layers and a first distance between each adjacent semiconductor layers. The method further includes providing a dielectric fin extending from the substrate where the dielectric fin is adjacent to the plurality of semiconductor layers and there is a second distance between an end of each of the semiconductor layers and a first sidewall of the dielectric fin. The second distance is greater than the first distance. Depositing a dielectric layer over the semiconductor layers and over the first sidewall of the dielectric fin. Forming a first metal layer over the dielectric layer on the semiconductor layers and on the first sidewall of the dielectric fin, wherein portions of the first metal layer disposed on and interposing adjacent semiconductor layers are merged together. Finally removing the first metal layer.

公开(公告)号：US11626327B2

公开(公告)日：2023-04-11

申请号：US17097578

申请日：2020-11-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Kuo-Cheng Chiang ,  Chung-Wei Hsu ,  Lung-Kun Chu ,  Jia-Ni Yu ,  Chih-Hao Wang ,  Mao-Lin Huang

IPC分类号： H01L21/70 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L29/49 ,  H01L27/092 ,  H01L21/308 ,  H01L21/033 ,  H01L21/28 ,  H01L29/78

摘要： A semiconductor device is provided. The semiconductor device includes a plurality of first semiconductor nanosheets spaced apart from each other and in a p-type device region, and a plurality of second semiconductor nanosheets spaced apart from each other and in an n-type device region. The semiconductor device includes an isolation structure formed at a boundary between the p-type and n-type device regions, and a first hard mask layer formed over the first semiconductor nanosheets. The semiconductor device also includes a second hard mask layer formed over the second semiconductor nanosheets, and a p-type work function layer surrounding each of the first semiconductor nanosheets and the first hard mask layer.

公开(公告)号：US20220140115A1

公开(公告)日：2022-05-05

申请号：US17087131

申请日：2020-11-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Lung-Kun Chu ,  Mao-Lin Huang ,  Chung-Wei Hsu ,  Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/8234

摘要： A method of fabricating a device includes providing a fin extending from a substrate, the fin having a plurality of semiconductor layers and a first distance between each adjacent semiconductor layers. The method further includes providing a dielectric fin extending from the substrate where the dielectric fin is adjacent to the plurality of semiconductor layers and there is a second distance between an end of each of the semiconductor layers and a first sidewall of the dielectric fin. The second distance is greater than the first distance. Depositing a dielectric layer over the semiconductor layers and over the first sidewall of the dielectric fin. Forming a first metal layer over the dielectric layer on the semiconductor layers and on the first sidewall of the dielectric fin, wherein portions of the first metal layer disposed on and interposing adjacent semiconductor layers are merged together. Finally removing the first metal layer.

公开(公告)号：US20220140097A1

公开(公告)日：2022-05-05

申请号：US17228922

申请日：2021-04-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Wei Hsu ,  Kuo-Cheng Chiang ,  Mao-Lin Huang ,  Lung-Kun Chu ,  Jia-Ni Yu ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC分类号： H01L29/423 ,  H01L29/786 ,  H01L27/092 ,  H01L21/8238

摘要： A structure has stacks of semiconductor layers over a substrate and adjacent a dielectric feature. A gate dielectric is formed wrapping around each layer and the dielectric feature. A first layer of first gate electrode material is deposited over the gate dielectric and the dielectric feature. The first layer on the dielectric feature is recessed to a first height below a top surface of the dielectric feature. A second layer of the first gate electrode material is deposited over the first layer. The first gate electrode material in a first region of the substrate is removed to expose a portion of the gate dielectric in the first region, while the first gate electrode material in a second region of the substrate is preserved. A second gate electrode material is deposited over the exposed portion of the gate dielectric and over a remaining portion of the first gate electrode material.

公开(公告)号：US12119391B2

公开(公告)日：2024-10-15

申请号：US18068388

申请日：2022-12-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Mao-Lin Huang ,  Lung-Kun Chu ,  Chung-Wei Hsu ,  Jia-Ni Yu ,  Chun-Fu Lu ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L21/823431 ,  H01L29/0673 ,  H01L29/7851

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The gate structure includes a gate dielectric layer, a first conductive layer over the first conductive layer. The gate structure includes a fill layer over the first conductive layer. The semiconductor device structure includes a protection layer formed over the fill layer, and a top surface of the gate dielectric layer is lower than a top surface of the protection layer and higher than a top surface of the first conductive layer.

公开(公告)号：US11756995B2

公开(公告)日：2023-09-12

申请号：US17459379

申请日：2021-08-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Lung-Kun Chu ,  Mao-Lin Huang ,  Chung-Wei Hsu ,  Jia-Ni Yu ,  Kuan-Lun Cheng ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC分类号： H01L29/06 ,  H01L21/8234 ,  H01L29/775 ,  H01L21/8238 ,  H01L21/822 ,  H01L27/06 ,  H01L27/088 ,  H01L27/092 ,  H01L29/08

CPC分类号： H01L29/0665 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0847

摘要： A semiconductor device structure, along with methods of forming such, are described. The structure includes first and second dielectric features and a first semiconductor layer disposed between the first and second dielectric features. The structure further includes an isolation layer disposed between the first and second dielectric features, and the isolation layer is in contact with the first and second dielectric features. The first semiconductor layer is disposed over the isolation layer. The structure further includes a gate dielectric layer disposed over the isolation layer and a gate electrode layer disposed over the gate dielectric layer. The gate electrode layer has an end extending to a level between a first plane defined by a first surface of the first semiconductor layer and a second plane defined by a second surface opposite the first surface.

公开(公告)号：US11615962B2

公开(公告)日：2023-03-28

申请号：US17167742

申请日：2021-02-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Wei Hsu ,  Kuo-Cheng Chiang ,  Mao-Lin Huang ,  Lung-Kun Chu ,  Jia-Ni Yu ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC分类号： H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/033 ,  H01L21/8238 ,  H01L29/66

摘要： A method includes providing a structure having a substrate and a stack of semiconductor layers over a surface of the substrate and spaced vertically one from another; forming an interfacial layer wrapping around each of the semiconductor layers; forming a high-k dielectric layer over the interfacial layer and wrapping around each of the semiconductor layers; and forming a capping layer over the high-k dielectric layer and wrapping around each of the semiconductor layers. With the capping layer wrapping around each of the semiconductor layers, the method further includes performing a thermal treatment to the structure, thereby increasing a thickness of the interfacial layer. After the performing of the thermal treatment, the method further includes removing the capping layer.

公开(公告)号：US20220320342A1

公开(公告)日：2022-10-06

申请号：US17218143

申请日：2021-03-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chung-Wei Hsu ,  Kuo-Cheng CHIANG ,  Mao-Lin Huang ,  LUNG-KUN CHU ,  Jia-Ni Yu ,  KUAN-LUN CHENG ,  CHIH-HAO WANG

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

摘要： A semiconductor device structure is provided. The device includes one or more first semiconductor layers, and a dipole layer surrounding each first semiconductor layer of the one or more first semiconductor layers, wherein the dipole layer comprises germanium. The structure also includes a capping layer surrounding and in contact with the dipole layer, wherein the capping layer comprises silicon, one or more second semiconductor layers disposed adjacent the one or more first semiconductor layers. The structure further includes a gate electrode layer surrounding each first semiconductor layer of the one or more first semiconductor layers and each second semiconductor layer of the one or more second semiconductor layers