JTAG BUS COMMUNICATION METHOD AND APPARATUS

    公开(公告)号:US20210215759A1

    公开(公告)日:2021-07-15

    申请号:US17213808

    申请日:2021-03-26

    Inventor: Lee D. Whetsel

    Abstract: The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.

    Switch coupling functional circuitry to via, scan cell contacting via

    公开(公告)号:US10969423B2

    公开(公告)日:2021-04-06

    申请号:US16407296

    申请日:2019-05-09

    Inventor: Lee D. Whetsel

    Abstract: An integrated circuit die includes a substrate of semiconductor material having a top surface, a bottom surface, and an opening through the substrate between the top surface and the bottom surface. A through silicon via (TSV) has a conductive body in the opening, has a top contact point coupled to the body at the top surface, and has a bottom contact point coupled to the body at the bottom surface. A scan cell has a serial input, a serial output, control inputs, a voltage reference input, a response input coupled to one of the contact points, and a stimulus output coupled to the other one of the contact points.

    Access ports, port selector with enable outputs, and TDI/TDO multiplexer

    公开(公告)号:US10948539B2

    公开(公告)日:2021-03-16

    申请号:US16522174

    申请日:2019-07-25

    Inventor: Lee D. Whetsel

    Abstract: The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal terminals of the device. The selecting and accessing of device access ports can be achieved when a single device is connected to the controller, when multiple devices are placed in a daisy-chain arrangement and connected to the controller, or when multiple devices are placed in a addressable parallel arrangement and connected to the controller. Additional embodiments are also provided and described in the disclosure.

    TEST ACCESS PORT WITH ADDRESS AND COMMAND CAPABILITY

    公开(公告)号:US20210033671A1

    公开(公告)日:2021-02-04

    申请号:US17076576

    申请日:2020-10-21

    Inventor: Lee D. Whetsel

    Abstract: The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a novel method and apparatus for inputting addresses for selecting device TAPs and for inputting commands for commanding circuitry within the device. The inputting of addresses or the inputting of addresses and commands is initiated by a control bit input on TDI that is recognized during the Run Test/Idle, Pause-DR or Pause-IR TAP states.

    Die testing using top surface test pads

    公开(公告)号:US10809295B2

    公开(公告)日:2020-10-20

    申请号:US16875628

    申请日:2020-05-15

    Abstract: Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.

    Functional, tap, trace circuitry with multiplexed tap, trace data output

    公开(公告)号:US10794953B2

    公开(公告)日:2020-10-06

    申请号:US16393352

    申请日:2019-04-24

    Inventor: Lee D. Whetsel

    Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

    DIRECT SCAN ACCESS JTAG
    39.
    发明申请

    公开(公告)号:US20200278394A1

    公开(公告)日:2020-09-03

    申请号:US16843535

    申请日:2020-04-08

    Inventor: Lee D. Whetsel

    Abstract: The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller.

    SCAN FRAME BASED TEST ACCESS MECHANISMS
    40.
    发明申请

    公开(公告)号:US20200278391A1

    公开(公告)日:2020-09-03

    申请号:US16876405

    申请日:2020-05-18

    Inventor: Lee D. Whetsel

    Abstract: Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The received scan frames contain stimulus data to be applied to circuitry within the device to be tested, a command for enabling a test control operation, and a frame marker bit to indicate the end of the scan frame pattern. The inputting of scan frames can occur continuously and simultaneous with a commanded test control operation.

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