DIE TESTING USING TOP SURFACE TEST PADS
    2.
    发明申请
    DIE TESTING USING TOP SURFACE TEST PADS 审中-公开
    使用顶表面测试垫进行DIE测试

    公开(公告)号:US20140225112A1

    公开(公告)日:2014-08-14

    申请号:US14258651

    申请日:2014-04-22

    Abstract: Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.

    Abstract translation: 晶片上的晶片的及时测试降低了制造IC的成本。 本公开描述了通过在模具的顶表面上添加测试焊盘来减少测试时间的模具测试结构和过程。 添加的测试垫允许测试仪同时探测和测试模具中的更多电路。 此外,添加的测试垫有助于减少访问和测试管芯内的电路所需的测试接线开销的量,从而减小管芯尺寸。

    Die testing using top surface test pads

    公开(公告)号:US10809295B2

    公开(公告)日:2020-10-20

    申请号:US16875628

    申请日:2020-05-15

    Abstract: Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.

    DIE TESTING USING TOP SURFACE TEST PADS
    4.
    发明申请

    公开(公告)号:US20200278389A1

    公开(公告)日:2020-09-03

    申请号:US16875628

    申请日:2020-05-15

    Abstract: Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.

    Test circuitry coupled to embedded circuit input/output unconnected to pads
    7.
    发明授权
    Test circuitry coupled to embedded circuit input/output unconnected to pads 有权
    耦合到未连接到焊盘的嵌入式电路输入/输出的测试电路

    公开(公告)号:US08742415B2

    公开(公告)日:2014-06-03

    申请号:US13894051

    申请日:2013-05-14

    Abstract: Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.

    Abstract translation: 晶片上的晶片的及时测试降低了制造IC的成本。 本公开描述了通过在模具的顶表面上添加测试焊盘来减少测试时间的模具测试结构和过程。 添加的测试垫允许测试仪同时探测和测试模具中的更多电路。 此外,添加的测试垫有助于减少访问和测试管芯内的电路所需的测试接线开销的量,从而减小管芯尺寸。

    IMPROVED DIE TESTING USING TOP SURFACE TEST PADS
    8.
    发明申请
    IMPROVED DIE TESTING USING TOP SURFACE TEST PADS 审中-公开
    使用顶部表面测试垫进行改进的DIE测试

    公开(公告)号:US20170003341A1

    公开(公告)日:2017-01-05

    申请号:US15267996

    申请日:2016-09-16

    Abstract: Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.

    Abstract translation: 晶片上的晶片的及时测试降低了制造IC的成本。 本公开描述了通过在模具的顶表面上添加测试焊盘来减少测试时间的模具测试结构和过程。 添加的测试垫允许测试仪同时探测和测试模具中的更多电路。 此外,添加的测试垫有助于减少访问和测试管芯内的电路所需的测试接线开销的量,从而减小管芯尺寸。

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