公开(公告)号：US10281522B2

公开(公告)日：2019-05-07

申请号：US15847156

申请日：2017-12-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel ,  Richard L. Antley

IPC: H01L23/58 ,  G01R31/28 ,  H01L21/66 ,  G01R1/04

Abstract: Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.

公开(公告)号：US20140225112A1

公开(公告)日：2014-08-14

申请号：US14258651

申请日：2014-04-22

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel ,  Richard L. Antley

IPC: H01L21/66

CPC classification number: G01R31/2886 ,  G01R1/0491 ,  H01L22/32 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.

Abstract translation: 晶片上的晶片的及时测试降低了制造IC的成本。 本公开描述了通过在模具的顶表面上添加测试焊盘来减少测试时间的模具测试结构和过程。 添加的测试垫允许测试仪同时探测和测试模具中的更多电路。 此外，添加的测试垫有助于减少访问和测试管芯内的电路所需的测试接线开销的量，从而减小管芯尺寸。

公开(公告)号：US10809295B2

公开(公告)日：2020-10-20

申请号：US16875628

申请日：2020-05-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel ,  Richard L. Antley

IPC: G01R31/28 ,  H01L21/66 ,  G01R1/04

Abstract: Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.

公开(公告)号：US20200278389A1

公开(公告)日：2020-09-03

申请号：US16875628

申请日：2020-05-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel ,  Richard L. Antley

IPC: G01R31/28 ,  H01L21/66 ,  G01R1/04

Abstract: Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.

公开(公告)号：US10690717B2

公开(公告)日：2020-06-23

申请号：US15267996

申请日：2016-09-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel ,  Richard L. Antley

IPC: H01L23/58 ,  G01R31/28 ,  H01L21/66 ,  G01R1/04

Abstract: Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.

公开(公告)号：US20150097186A1

公开(公告)日：2015-04-09

申请号：US14570425

申请日：2014-12-15

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel ,  Richard L. Antley

IPC: H01L21/66

CPC classification number: G01R31/2886 ,  G01R1/0491 ,  H01L22/32 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.

公开(公告)号：US08742415B2

公开(公告)日：2014-06-03

申请号：US13894051

申请日：2013-05-14

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel ,  Richard L. Antley

IPC: H01L23/58

CPC classification number: G01R31/2886 ,  G01R1/0491 ,  H01L22/32 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.

Abstract translation: 晶片上的晶片的及时测试降低了制造IC的成本。 本公开描述了通过在模具的顶表面上添加测试焊盘来减少测试时间的模具测试结构和过程。 添加的测试垫允许测试仪同时探测和测试模具中的更多电路。 此外，添加的测试垫有助于减少访问和测试管芯内的电路所需的测试接线开销的量，从而减小管芯尺寸。

公开(公告)号：US20170003341A1

公开(公告)日：2017-01-05

申请号：US15267996

申请日：2016-09-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel ,  Richard L. Antley

IPC: G01R31/28 ,  G01R1/04 ,  H01L21/66

Abstract: Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.

Abstract translation: 晶片上的晶片的及时测试降低了制造IC的成本。 本公开描述了通过在模具的顶表面上添加测试焊盘来减少测试时间的模具测试结构和过程。 添加的测试垫允许测试仪同时探测和测试模具中的更多电路。 此外，添加的测试垫有助于减少访问和测试管芯内的电路所需的测试接线开销的量，从而减小管芯尺寸。

公开(公告)号：US20180106858A1

公开(公告)日：2018-04-19

申请号：US15847156

申请日：2017-12-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel ,  Richard L. Antley

IPC: G01R31/28 ,  H01L21/66 ,  G01R1/04

CPC classification number: G01R31/2886 ,  G01R1/0491 ,  H01L22/32 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.

公开(公告)号：US09472478B2

公开(公告)日：2016-10-18

申请号：US14946061

申请日：2015-11-19

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel ,  Richard L. Antley

IPC: H01L23/58 ,  H01L21/66

CPC classification number: G01R31/2886 ,  G01R1/0491 ,  H01L22/32 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.