公开(公告)号：US20170289034A1

公开(公告)日：2017-10-05

申请号：US15622936

申请日：2017-06-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Patrick W. Bosshart ,  Hun-Seok Kim

IPC: H04L12/741

CPC classification number: H04L45/74

Abstract: A packet processing block. The block comprises an input for receiving data in a packet header vector, the vector comprising data values representing information for a packet. The block also comprises circuitry for performing packet match operations in response to at least a portion of the packet header vector and data stored in a match table, and circuitry for performing one or more actions in response to a match detected by the circuitry for performing packet match operations and according to information stored in an action table. Each of said match table and said action table comprise one or more memories selected from a pool of unit memories, wherein each memory in the pool of unit memories is configurable to operate as either a match memory or an action memory.

公开(公告)号：US09712439B2

公开(公告)日：2017-07-18

申请号：US14193177

申请日：2014-02-28

Applicant: Texas Instruments Incorporated

Inventor： Patrick W. Bosshart ,  Hun-Seok Kim

IPC: H04L12/741

CPC classification number: H04L45/74

Abstract: A packet processing block. The block comprises an input for receiving data in a packet header vector, the vector comprising data values representing information for a packet. The block also comprises circuitry for performing packet match operations in response to at least a portion of the packet header vector and data stored in a match table, and circuitry for performing one or more actions in response to a match detected by the circuitry for performing packet match operations and according to information stored in an action table. Each of said match table and said action table comprise one or more memories selected from a pool of unit memories, wherein each memory in the pool of unit memories is configurable to operate as either a match memory or an action memory.

公开(公告)号：US09484095B2

公开(公告)日：2016-11-01

申请号：US14618057

申请日：2015-02-10

Applicant: Texas Instruments Incorporated

Inventor： Patrick W. Bosshart

IPC: G11C15/00 ,  G11C15/04

CPC classification number: G11C15/04

Abstract: An embodiment of the invention includes a Ternary Content Addressable Memory (TCAM) that includes a group of TCAM block. Each TCAM block stores a number of match entries. Each TCAM block is ranked in priority order. The TCAM also includes a group of TCAM headpointers. There is a TCAM headpointer coupled to each TCAM block. The TCAM headpointer indicates the highest priority match in the group of match entries in a TCAM block. The match entries within a TCAM block are prioritized in circular priority order starting from the highest priority match.

Abstract translation: 本发明的实施例包括包括一组TCAM块的三进制内容可寻址存储器（TCAM）。 每个TCAM块存储多个匹配条目。 每个TCAM块按优先顺序排列。 TCAM还包括一组TCAM头部指针。 有一个连接到每个TCAM块的TCAM头指针。 TCAM头指针指示TCAM块中的匹配项组中的最高优先级匹配。 TCAM块中的匹配条目以最高优先级匹配开始以循环优先级顺序进行优先级排序。

公开(公告)号：US09087586B2

公开(公告)日：2015-07-21

申请号：US14205812

申请日：2014-03-12

Applicant: Texas Instruments Incorporated

Inventor： Patrick W. Bosshart

IPC: G11C15/00 ,  G11C15/04

CPC classification number: G11C15/04

Abstract: An embodiment of the invention includes first and second Ternary Content Addressable Memories (TCAMs), a first vector, and TCAM match-merge unit. Each of the TCAMs includes a plurality of words, stores TCAM match entries and outputs a TCAM match signal for each word in the plurality of words. The first vector includes first TCAM group enable register bits. An enabling value on the first TCAM register bit indicates that the first TCAM match signal and the neighboring first TCAM match are in the same TCAM group. The TCAM match-merge unit receives the first TCAM match signal from each of the words and the first vector and outputs a first TCAM group match signal for each of the words. The TCAM match-merge unit outputs a match indication when any of the TCAM match signals indicate a match and outputs a mismatch when none of the TCAM match signals match.

Abstract translation: 本发明的实施例包括第一和第二三进制内容可寻址存储器（TCAM），第一向量和TCAM匹配合并单元。 每个TCAM包括多个字，存储TCAM匹配项，并输出多个单词中的每个单词的TCAM匹配信号。 第一个向量包括第一个TCAM组使能寄存器位。 第一个TCAM寄存器位的使能值表示第一个TCAM匹配信号和相邻的第一个TCAM匹配位于相同的TCAM组中。 TCAM匹配合并单元从每个单词和第一矢量接收第一TCAM匹配信号，并输出每个单词的第一TCAM组匹配信号。 当任何TCAM匹配信号指示匹配时，TCAM匹配合并单元输出匹配指示，并且当没有TCAM匹配信号匹配时输出失配。

公开(公告)号：US20140328344A1

公开(公告)日：2014-11-06

申请号：US14168202

申请日：2014-01-30

Applicant: Texas Instruments Incorporated

Inventor： Patrick W. Bosshart

IPC: H04L12/741 ,  H04L12/707 ,  H04L12/771 ,  H04L29/06

CPC classification number: H04L45/74 ,  H04L45/24 ,  H04L45/56

Abstract: An embodiment of the invention includes a plurality of tables in a hardware network for performing packet processing. Each table in the plurality of tables includes a table declaration. The table declaration includes a first set of fields used for input matching and a second set of fields used as inputs for action processing. A first table is selected from the plurality of tables. Successor tables to the first table are selected from the plurality of tables. There is a third set of fields for each successor table of the successor tables. The contents of the third set of fields are output fields where the output fields are modified by the first table when a next table of the first table is the successor table of the first table.

Abstract translation: 本发明的实施例包括用于执行分组处理的硬件网络中的多个表。 多个表中的每个表包括表声明。 表格声明包括用于输入匹配的第一组字段和用作动作处理的输入的第二组字段。 从多个表中选择第一表。 从多个表中选择到第一表的后继表。 后续表的每个后继表的第三组字段。 当第一个表的下一个表是第一个表的后继表时，第三组字段的内容是输出字段，其中输出字段被第一个表修改。

公开(公告)号：US20140241361A1

公开(公告)日：2014-08-28

申请号：US14193177

申请日：2014-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Patrick W. Bosshart ,  Hun-Seok Kim

IPC: H04L12/743

CPC classification number: H04L45/74

Abstract: A packet processing block. The block comprises an input for receiving data in a packet header vector, the vector comprising data values representing information for a packet. The block also comprises circuitry for performing packet match operations in response to at least a portion of the packet header vector and data stored in a match table, and circuitry for performing one or more actions in response to a match detected by the circuitry for performing packet match operations and according to information stored in an action table. Each of said match table and said action table comprise one or more memories selected from a pool of unit memories, wherein each memory in the pool of unit memories is configurable to operate as either a match memory or an action memory.

Abstract translation: 一个数据包处理块。 该块包括用于在分组报头向量中接收数据的输入，该矢量包括表示分组信息的数据值。 该块还包括用于响应于分组报头向量和存储在匹配表中的数据的至少一部分来执行分组匹配操作的电路，以及用于响应于由用于执行分组的电路检测到的匹配而执行一个或多个动作的电路 匹配操作和根据存储在操作表中的信息。 所述匹配表和所述动作表中的每一个包括从单元存储器池中选择的一个或多个存储器，其中单元存储器池中的每个存储器可配置为作为匹配存储器或动作存储器操作。

公开(公告)号：US20140219294A1

公开(公告)日：2014-08-07

申请号：US14025177

申请日：2013-09-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Patrick W. Bosshart

IPC: H04L45/749

CPC classification number: H04L45/741 ,  H04L61/251 ,  H04L61/6004 ,  H04L61/6095

Abstract: In an embodiment of the invention, a method of performing a byte-rotate-merge on computer hardware is discussed. Byte-rotating is performed on first and second source operands and are byte-rotated by first and second rotation constants respectively. The first byte-rotate output and the second byte-rotate output are merged. Bytes from the first byte-rotate output are output to a byte-rotate-merge output when control bits from a byte-mask are logical ones. Bytes from the second byte-rotate output are output to a byte-rotate-merge output when control bits from the byte-mask are logical zeros.

Abstract translation: 在本发明的实施例中，讨论了在计算机硬件上执行字节旋转合并的方法。 在第一和第二源操作数上执行字节旋转，并分别由第一和第二旋转常数进行字节旋转。 第一个字节旋转输出和第二个字节旋转输出合并。 来自字节掩码的控制位是逻辑1时，来自第一个字节旋转输出的字节被输出到一个字节旋转合并输出。 来自字节掩码的控制位为逻辑0时，来自第二字节旋转输出的字节被输出到字节旋转合并输出。