公开(公告)号：US20250112794A1

公开(公告)日：2025-04-03

申请号：US18981187

申请日：2024-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Lien Linus LU ,  Cheng-En LEE

IPC: H04L9/32 ,  G06F21/75 ,  G11C11/419 ,  H03K3/03

Abstract: Disclosed is a physical unclonable function generator circuit and method. In one embodiment, physical unclonable function (PUF) generator includes: a PUF cell array that comprises a plurality of bit cells, wherein each of the plurality of bit cells comprises at least two access transistors, at least one enable transistor, and at least two storage nodes, wherein the at least two storage nodes are pre-configured with substantially the same voltages allowing each of the plurality of bit cells having a first metastable logical state; a PUF control circuit coupled to the PUF cell array, wherein the PUF control circuit is configured to access the plurality of bit cells to determine second logical states by turning on the at least one enable transistor and turning off the at least two access transistors of each of the plurality of bit cells, and based on the second logical states of the plurality of bit cells, to generate a PUF output; and a noise injector coupled to the PUF control circuit and the PUF cell array, wherein the noise injector is configured to create stressed operation conditions to evaluate stability of the plurality of bit cells.

公开(公告)号：US20240396750A1

公开(公告)日：2024-11-28

申请号：US18790296

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Lien Linus LU ,  Cormac Michael O'CONNELL

IPC: H04L9/32

Abstract: Disclosed is a physical unclonable function generator circuit and testing method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, wherein each of the plurality of columns is coupled to at least two pre-discharge transistors, and each of the plurality of bit cells comprises at least one enable transistor, at least two access transistors, and at least two storage nodes, and a PUF control circuit coupled to the PUF cell array, wherein the PUF control circuit is configured to access the plurality of bit cells to pre-charge the at least two storage nodes with substantially the same voltages allowing each of the plurality of bit cell having a first metastable logical state; to determine a second logical state; and based on the determined second logical states of the plurality of bit cells, to generate a PUF signature.

公开(公告)号：US20240371674A1

公开(公告)日：2024-11-07

申请号：US18769250

申请日：2024-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Lien Linus LU ,  Cormac Michael O'CONNELL

IPC: H01L21/68 ,  B25J9/16 ,  B25J11/00 ,  H01L21/67 ,  H01L21/673

Abstract: Disclosed is a physical unclonable function generator circuit and method. In one embodiment, a physical unclonable function (PUF) generator comprising: a plurality of PUF cells, wherein each of the plurality of PUF cells comprises a first MOS transistor and a second MOS transistor, wherein terminal S of the first MOS transistor is connected to terminal D of the second MOS transistor at a dynamic node, terminal D of the first MOS transistor is coupled to a first bus and terminal G of the first NMOS transistor is coupled to a second bus, and terminals S and G of the second NMOS transistor are coupled to ground; a plurality of dynamic flip-flop (DFF) circuits wherein each of the plurality of DFF circuits is coupled to each of the plurality of PUF cells respectively; a population count circuit coupled to the plurality of DFF circuits; and an evaluation logic circuit having an input coupled to the population count circuit and an output coupled to the plurality of DFF circuits.

公开(公告)号：US20230388135A1

公开(公告)日：2023-11-30

申请号：US18232336

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Lien Linus LU ,  Cormac Michael O'Connell

IPC: H04L9/32

CPC classification number: H04L9/3278 ,  H04L9/3247 ,  H04L2209/12

Abstract: Disclosed is a physical unclonable function generator circuit and testing method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, wherein each of the plurality of columns is coupled to at least two pre-discharge transistors, and each of the plurality of bit cells comprises at least one enable transistor, at least two access transistors, and at least two storage nodes, and a PUF control circuit coupled to the PUF cell array, wherein the PUF control circuit is configured to access the plurality of bit cells to pre-charge the at least two storage nodes with substantially the same voltages allowing each of the plurality of bit cell having a first metastable logical state; to determine a second logical state; and based on the determined second logical states of the plurality of bit cells, to generate a PUF signature.

公开(公告)号：US20220343032A1

公开(公告)日：2022-10-27

申请号：US17859513

申请日：2022-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Lien Linus LU

IPC: G06F21/75 ,  H04L9/00 ,  G11C11/412 ,  G11C11/418 ,  H03K19/003 ,  G11C11/419

Abstract: Methods and apparatus for protecting a physical unclonable function (PUF) generator are disclosed. In one example, a PUF generator is disclosed. The PUF generator includes a PUF cell array, a PUF control circuit and a reset circuit. The PUF cell array comprises a plurality of bit cells. Each of the plurality of bit cells is configurable into at least two different stable states. The PUF control circuit is coupled to the PUF cell array and is configured to access each of the plurality of bit cells to determine one of the at least two different stable states upon a power-up of the plurality of bit cells, and generate a PUF signature based on the determined stable states of the plurality of bit cells. The reset circuit is coupled to the PUF cell array and is configured to set the plurality of bit cells to represent their initialization data based on an indication of a voltage tempering event of a supply voltage of the PUF cell array.

公开(公告)号：US20210211312A1

公开(公告)日：2021-07-08

申请号：US17208894

申请日：2021-03-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Lien Linus LU ,  Chen-En Lee

IPC: H04L9/32 ,  G06F21/75 ,  G11C11/419

Abstract: Disclosed is a physical unclonable function generator circuit and method. In one embodiment, physical unclonable function (PUF) generator includes: a PUF cell array that comprises a plurality of bit cells, wherein each of the plurality of bit cells comprises at least two access transistors, at least one enable transistor, and at least two storage nodes, wherein the at least two storage nodes are pre-configured with substantially the same voltages allowing each of the plurality of bit cells having a first metastable logical state; a PUF control circuit coupled to the PUF cell array, wherein the PUF control circuit is configured to access the plurality of bit cells to determine second logical states by turning on the at least one enable transistor and turning off the at least two access transistors of each of the plurality of bit cells, and based on the second logical states of the plurality of bit cells, to generate a PUF output; and a noise injector coupled to the PUF control circuit and the PUF cell array, wherein the noise injector is configured to create stressed operation conditions to evaluate stability of the plurality of bit cells.

公开(公告)号：US20210083887A1

公开(公告)日：2021-03-18

申请号：US17107816

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Shih-Lien Linus LU ,  Cormac Michael O'CONNELL

IPC: H04L9/32

Abstract: Disclosed is a physical unclonable function generator circuit and testing method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, wherein each of the plurality of columns is coupled to at least two pre-discharge transistors, and each of the plurality of bit cells comprises at least one enable transistor, at least two access transistors, and at least two storage nodes, and a PUF control circuit coupled to the PUF cell array, wherein the PUF control circuit is configured to access the plurality of bit cells to pre-charge the at least two storage nodes with substantially the same voltages allowing each of the plurality of bit cell having a first metastable logical state; to determine a second logical state; and based on the determined second logical states of the plurality of bit cells, to generate a PUF signature.

公开(公告)号：US20210055166A1

公开(公告)日：2021-02-25

申请号：US16549636

申请日：2019-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lorraine WANG ,  Shih-Lien Linus LU

IPC: G01K3/00 ,  G01K7/02

Abstract: A temperature sensor is disclosed that determines whether the temperature of an integrated circuit (IC) is within a normal temperature range. The temperature sensor includes a low threshold monitor circuit and a high threshold monitor circuit. The low threshold monitor circuit senses whether the temperature of the IC is above or below a minimum temperature threshold. The high threshold monitor circuit configured senses whether the temperature of an integrated circuit (IC) is above or below a maximum temperature threshold. The low threshold monitor circuit includes a first pair of conductive lines, each having a different temperature coefficient of resistance (TCR) from the other; where the minimum temperature threshold is determined by an intersection of a first TCR and a second TCR that are associated with the first pair of conductive lines. The high threshold monitor circuit includes a second pair of conductive lines, each having a different TCR from the other and also different from that of the first pair of conductive lines; where the maximum temperature threshold is determined by an intersection of a third TCR and a fourth TCR associated that are with the second pair of conductive lines.

公开(公告)号：US20200020364A1

公开(公告)日：2020-01-16

申请号：US16160397

申请日：2018-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Che TSAI ,  Cheng Hung LEE ,  Shih-Lien Linus LU ,  Yi-Ju CHEN

IPC: G11C7/08 ,  G11C7/12 ,  H04L9/32

Abstract: A memory storage device is fabricated using a semiconductor fabrication process. Often times, manufacturing variations and/or misalignment tolerances present within the semiconductor fabrication process can cause the memory storage device to differ from other memory storage devices similarly designed and fabricated by the semiconductor fabrication process. For example, uncontrollable random physical processes in the semiconductor fabrication process can cause small differences, such as differences in doping concentrations, oxide thicknesses, channel lengths, structural widths, and/or parasitics to provide some examples, between these memory storage devices. These small differences can cause bitlines within the memory storage device to be physically unique with no two bitlines being identical. As a result, the uncontrollable random physical processes in the semiconductor fabrication process can cause electronic data read from the memory storage device to propagate along the bitlines at different rates. This physical uniqueness of the bitlines can be utilized to implement a physical unclonable function (PUF) allowing the memory storage device to be differentiated from other memory storage devices similarly designed and fabricated by the semiconductor fabrication process.

公开(公告)号：US20190378575A1

公开(公告)日：2019-12-12

申请号：US16004199

申请日：2018-06-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Lien Linus LU

IPC: G11C16/22 ,  G06F12/14 ,  H04L9/32

Abstract: Disclosed is a physical unclonable function generator circuit and testing method. In one embodiment, a testing method for physical unclonable function (PUF) generator includes: verifying a functionality of a PUF generator by writing preconfigured logical states to and reading output logical states from a plurality of bit cells in a PUF cell array; determining a first number of first bit cells in the PUF cell array, wherein the output logical states of the first bit cells are different from the preconfigured logical states; if the first number of first bit cells is less than a first predetermined number, generating a first map under a first set of operation conditions using the PUF generator and a masking circuit, wherein the first map comprises at least one stable bit cells and at least one unstable bit cell; generating a second map under a second set of operation conditions using the PUF generator and the masking circuit, wherein the second map comprises at least one stable bit cells and at least one unstable bit cell; determining a second number of second bit cells, wherein the second bit cells are stable in the first map and unstable in the second map using a Built-in Self Test (BIST) engine; if the second number of second bit cells is determined to be zero, determining a third number of third bit cells using the BIST engine, wherein the third bit cells are stable in the first map and stable in the second map; and if the third number of third bit cells are greater than a second preconfigured number, the PUF generator is determined as a qualified PUF generator.