-
公开(公告)号：US20240154823A1
公开(公告)日：2024-05-09
申请号：US18412344
申请日：2024-01-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shih-Lien Linus LU , Cheng-En LEE
CPC classification number: H04L9/3278 , G06F21/75 , H03K3/0315
Abstract: Disclosed is a physical unclonable function generator circuit and method. In one embodiment, physical unclonable function (PUF) generator includes: a PUF cell array that comprises a plurality of bit cells, wherein each of the plurality of bit cells comprises at least two access transistors, at least one enable transistor, and at least two storage nodes, wherein the at least two storage nodes are pre-configured with substantially the same voltages allowing each of the plurality of bit cells having a first metastable logical state; a PUF control circuit coupled to the PUF cell array, wherein the PUF control circuit is configured to access the plurality of bit cells to determine second logical states by turning on the at least one enable transistor and turning off the at least two access transistors of each of the plurality of bit cells, and based on the second logical states of the plurality of bit cells, to generate a PUF output; and a noise injector coupled to the PUF control circuit and the PUF cell array, wherein the noise injector is configured to create stressed operation conditions to evaluate stability of the plurality of bit cells.
-
公开(公告)号：US20210359869A1
公开(公告)日：2021-11-18
申请号：US17390467
申请日：2021-07-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shih-Lien Linus LU
IPC: H04L9/32 , H03K19/0944
Abstract: An integrated circuit is fabricated using a semiconductor fabrication process. One or more uncontrollable random physical processes in the semiconductor fabrication process can cause small differences between the integrated circuit and other similarly designed integrated circuit. These small differences can cause transistors of the integrated circuit to have different threshold voltages. The integrated circuit can use these different threshold voltages to quantify its physical uniqueness to differentiate itself from other integrated circuits similarly designed and fabricated by the semiconductor fabrication process.
-
公开(公告)号：US20200052912A1
公开(公告)日：2020-02-13
申请号：US16101969
申请日：2018-08-13
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shih-Lien Linus LU
Abstract: Disclosed is a device and method to secure software update information for authorized entities. In one embodiment, a device for receiving secured software update information from a server, the device includes: a physical uncolonable function (PUF) information generator, comprising a PUF cell array, configured to generate PUF information, wherein the PUF information comprises at least one PUF response output, wherein the at least one PUF response output is used to encrypt the software update information on the server so as to generate encrypted software update information; a first encrypter, configured to encrypt the PUF information from the PUF information generator using one of at least one public key from the server so as to generate encrypted PUF information; and a second encrypter, configured to decrypt the encrypted software update information using one of the at least one PUF response output so as to obtain the software update information.
-
4.发明申请公开(公告)号：US20190379381A1
公开(公告)日：2019-12-12
申请号：US16230088
申请日：2018-12-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shih-Lien Linus LU , Cheng-En LEE , Jui-Che TSAI
IPC: H03K19/177 , G06F12/14 , G06F21/72 , H04L9/32 , G11C16/22
Abstract: Disclosed is a physical unclonable function generator circuit and method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells, wherein each of the plurality of bit cells comprises at least two inverters, at least one floating capacitor, at least two dynamic nodes, wherein the at least one floating capacitor is coupled between a first inverter at a first dynamic node and a second inverter at a second dynamic node; a PUF controller coupled to the PUF cell array, wherein the PUF controller is configured to charge the first dynamic nodes through the respective first inverters in the plurality of bit cells; and a finite state machine coupled to the PUF cell array configured to determine voltage levels on the second dynamic nodes through the respective second inverters in the plurality of bit cells to determine first logical states of the plurality of bit cells at at least one sampling time and generate a PUF signature.
-
公开(公告)号：US20180150398A1
公开(公告)日：2018-05-31
申请号：US15370113
申请日：2016-12-06
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shih-Lien Linus LU
IPC: G06F12/0846
CPC classification number: G06F12/0864 , G06F11/1423 , G06F12/0846 , G06F2212/1016 , G06F2212/1032 , G06F2212/601 , G06F2212/608
Abstract: An integrated circuit (IC) is provided. The IC includes a cache memory and an address decoder. The cache memory is divided into a plurality of groups. The address decoder provides a physical address according to an access address. When the access address corresponds to a specific group of the groups of the cache memory, the address decoder changes the access address to provide the physical address, and when the access address corresponds to one of the groups other than the specific group in the cache memory, the address decoder assigns the access address as the physical address.
-
Patent Agency Ranking
公开(公告)号：US20180096172A1
公开(公告)日：2018-04-05
申请号：US15284876
申请日：2016-10-04
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shih-Lien Linus LU
IPC: G06F21/86 , G11C11/419 , G06F21/78 , G06F21/60
CPC classification number: G06F21/86 , G06F21/79 , G06F2221/2143 , G11C5/145 , G11C7/20 , G11C8/08 , G11C11/418 , G11C11/419
Abstract: A memory device is disclosed. The memory device includes a memory bit array comprising a plurality of memory bits, wherein each memory bit is configured to present an initial logic state when the memory device is powered on, and an erasion circuit, coupled to the memory bit array, and configured to alter an intrinsic characteristic of at least one of the memory bits so as to alter the initial logic state of the at least one memory bit.
-
公开(公告)号：US20240214226A1
公开(公告)日：2024-06-27
申请号：US18602593
申请日：2024-03-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Jui-Che TSAI , Shih-Lien Linus LU , Cheng Hung LEE , Chia-En HUANG
IPC: H04L9/32 , G11C7/06 , G11C11/4091 , H04L9/08
CPC classification number: H04L9/3278 , G11C7/06 , G11C11/4091 , H04L9/0861
Abstract: Disclosed is an input/output circuit for a physical unclonable function generator circuit. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, and at least one input/output (I/O) circuit each coupled to at least two neighboring columns of the PUF cell array, wherein the at least one I/O circuit each comprises a sense amplifier (SA) with no cross-coupled pair of transistors, wherein the SA comprises two cross-coupled inverters with no access transistor and a SA enable transistor, and wherein the at least one I/O circuit each is configured to access and determine logical states of at least two bit cells in the at least two neighboring columns; and based on the determined logical states of the plurality of bit cells, to generate a PUF signature.
-
公开(公告)号：US20240202374A1
公开(公告)日：2024-06-20
申请号：US18404355
申请日：2024-01-04
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shih-Lien Linus LU
IPC: G06F21/75 , G11C11/412 , G11C11/418 , G11C11/419 , H03K19/003 , H04L9/00 , H04L9/32
CPC classification number: G06F21/755 , G11C11/412 , G11C11/418 , G11C11/419 , H03K19/00315 , H04L9/002 , H04L9/3278
Abstract: Methods and apparatus for protecting a physical unclonable function (PUF) generator are disclosed. In one example, a PUF generator is disclosed. The PUF generator includes a PUF cell array, a PUF control circuit and a reset circuit. The PUF cell array comprises a plurality of bit cells. Each of the plurality of bit cells is configurable into at least two different stable states. The PUF control circuit is coupled to the PUF cell array and is configured to access each of the plurality of bit cells to determine one of the at least two different stable states upon a power-up of the plurality of bit cells, and generate a PUF signature based on the determined stable states of the plurality of bit cells. The reset circuit is coupled to the PUF cell array and is configured to set the plurality of bit cells to represent their initialization data based on an indication of a voltage tempering event of a supply voltage of the PUF cell array.
-
公开(公告)号：US20230049649A1
公开(公告)日：2023-02-16
申请号：US17976116
申请日：2022-10-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shih-Lien Linus LU
Abstract: Disclosed is a device and method to secure software update information for authorized entities. In one embodiment, a device for receiving secured software update information from a server, the device includes: a physical unclonable function (PUF) information generator, comprising a PUF cell array, configured to generate PUF information, wherein the PUF information comprises at least one PUF response output, wherein the at least one PUF response output is used to encrypt the software update information on the server so as to generate encrypted software update information; a first encrypter, configured to encrypt the PUF information from the PUF information generator using one of at least one public key from the server so as to generate encrypted PUF information; and a second encrypter, configured to decrypt the encrypted software update information using one of the at least one PUF response output so as to obtain the software update information.
-
公开(公告)号：US20230022719A1
公开(公告)日：2023-01-26
申请号：US17960018
申请日：2022-10-04
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shih-Lien Linus LU
Abstract: Disclosed is a physical unclonable function generator circuit and testing method. In one embodiment, a testing method for physical unclonable function (PUF) generator includes: verifying a functionality of a PUF generator by writing preconfigured logical states to and reading output logical states from a plurality of bit cells in a PUF cell array; determining a first number of first bit cells in the PUF cell array, wherein the output logical states of the first bit cells are different from the preconfigured logical states; when the first number of first bit cells is less than a first predetermined number, generating a first map under a first set of operation conditions using the PUF generator and a masking circuit, generating a second map under a second set of operation conditions using the PUF generator and the masking circuit, determining a second number of second bit cells, wherein the second bit cells are stable in the first map and unstable in the second map; when the second number of second bit cells is determined to be zero, determining a third number of third bit cells, wherein the third bit cells are stable in the first map and stable in the second map; and when the third number of third bit cells are greater than a second preconfigured number, the PUF generator is determined as a qualified PUF generator.
-
-
-
-
-
-
-
-
-
Search Results
53
records
(took 0.021 seconds)
