公开(公告)号：US11621271B2

公开(公告)日：2023-04-04

申请号：US17177164

申请日：2021-02-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu

IPC: H01L21/28 ,  H01L27/1157 ,  H01L29/792 ,  H01L29/423 ,  H01L29/66

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell includes a memory gate, a dielectric layer, two charge trapping layers and two selective gates. The memory gate is disposed on a substrate. The two charge trapping layers are at two ends of the dielectric layer, and the charge trapping layers and the dielectric layer are sandwiched by the substrate and the memory gate. The two selective gates are disposed at two opposite sides of the memory gate, thereby constituting a two bit memory cell. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.

公开(公告)号：US20220262808A1

公开(公告)日：2022-08-18

申请号：US17706577

申请日：2022-03-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu

IPC: H01L27/1157 ,  H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  H01L29/423

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell includes a memory gate, a dielectric layer, two charge trapping layers and two selective gates. The memory gate is disposed on a substrate. The two charge trapping layers are at two ends of the dielectric layer, and the charge trapping layers and the dielectric layer are sandwiched by the substrate and the memory gate. The two selective gates are disposed at two opposite sides of the memory gate, thereby constituting a two bit memory cell. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.

公开(公告)号：US20220262806A1

公开(公告)日：2022-08-18

申请号：US17177164

申请日：2021-02-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu

IPC: H01L27/1157 ,  H01L29/792 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell includes a memory gate, a dielectric layer, two charge trapping layers and two selective gates. The memory gate is disposed on a substrate. The two charge trapping layers are at two ends of the dielectric layer, and the charge trapping layers and the dielectric layer are sandwiched by the substrate and the memory gate. The two selective gates are disposed at two opposite sides of the memory gate, thereby constituting a two bit memory cell. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.

公开(公告)号：US11387337B2

公开(公告)日：2022-07-12

申请号：US17134131

申请日：2020-12-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Sung Huang ,  Shen-De Wang ,  Chia-Ching Hsu ,  Wang Xiang

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/792

Abstract: A memory device includes a main cell on a substrate, a first reference cell adjacent to one side of the main cell, and a second reference cell adjacent to another side of the main cell. Preferably, the main cell includes a first gate electrode on the substrate, a second gate electrode on one side of the first gate electrode and covering a top surface of the first gate electrode, a first charge trapping layer between the first gate electrode and the second gate electrode and including a first oxide-nitride-oxide (ONO) layer, a third gate electrode on another side of the first gate electrode and covering the top surface of the first gate electrode, and a second charge trapping layer between the first gate electrode and the third gate electrode and including a second ONO layer.

公开(公告)号：US20170084622A1

公开(公告)日：2017-03-23

申请号：US14856577

申请日：2015-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu ,  Ko-Chi Chen ,  Shen-De Wang

IPC: H01L27/115

CPC classification number: H01L27/11529 ,  H01L27/11524 ,  H01L27/11531 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11573

Abstract: A semiconductor device includes a substrate with a memory region and a logic region, a logic gate stack, and a non-volatile gate stack. The substrate has a recess disposed in the memory region. The logic gate stack is disposed in the logic region and has a first top surface. The non-volatile gate stack is disposed in the recess and has a second top surface. The second top surface is lower than the first top surface by a step height.