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公开(公告)号：US11864473B2
公开(公告)日：2024-01-02
申请号：US17404934
申请日：2021-08-17
Applicant: United Microelectronics Corp.
Inventor： Wen-Jen Wang , Chun-Hung Cheng , Chuan-Fu Wang
CPC classification number: H10N70/021 , H10B63/80 , H10N70/063 , H10N70/068 , H10N70/841 , H10N70/8833
Abstract: Provided is a resistive random-access memory device, including a dielectric layer located on a substrate, a first electrode which is a column located on the dielectric layer, a second electrode covering a top surface and a sidewall of the first electrode, and a variable resistance layer sandwiched between the top surface of the first electrode and the second electrode and between the sidewall of the first electrode and the second electrode and located between the second electrode and the dielectric layer.
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公开(公告)号：US11437436B2
公开(公告)日：2022-09-06
申请号：US17084609
申请日：2020-10-29
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wen-Jen Wang , Chun-Hung Cheng , Chuan-Fu Wang
Abstract: A semiconductor device includes a substrate having a memory region and a logic region. A first dielectric layer is disposed on the substrate. A first conductive structure and a second conductive structure are formed in the first dielectric layer and respectively on the memory region and the logic region of the substrate. A memory cell is disposed on the first dielectric layer and directly contacts a top surface of the first conductive structure. A first cap layer is formed on the first dielectric layer and continuously covers a top surface and a sidewall of the memory cell and a top surface of the second conductive structure. A second dielectric layer is formed on the first cap. A third conductive structure is formed in the second dielectric layer and penetrates through the first cap layer to contacts the memory cell.
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公开(公告)号：US20220130903A1
公开(公告)日：2022-04-28
申请号：US17571519
申请日：2022-01-09
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wen-Jen Wang , Chun-Hung Cheng , Chuan-Fu Wang
Abstract: An RRAM structure includes a substrate. The substrate is divided into a memory cell region and a logic device region. A metal plug is disposed within the memory cell region. An RRAM is disposed on and contacts the metal plug. The RRAM includes a top electrode, a variable resistive layer, and a bottom electrode. The variable resistive layer is disposed between the top electrode and the bottom electrode. The variable resistive layer includes a first bottom surface. The bottom electrode includes a first top surface. The first bottom surface and the first top surface are coplanar. The first bottom surface only overlaps and contacts part of the first top surface.
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公开(公告)号：US10707225B2
公开(公告)日：2020-07-07
申请号：US16792847
申请日：2020-02-17
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wen-Jen Wang , Chun-Hung Cheng , Chuan-Fu Wang
IPC: H01L27/115 , H01L27/11568 , H01L29/792 , H01L21/28
Abstract: A method for fabricating a semiconductor memory device is disclosed. A substrate having a main surface is provided. A memory gate is formed on the main surface of the substrate. The memory has a first sidewall and a second sidewall opposite to the first sidewall. A control gate is formed in proximity to the memory gate. The control gate has a third sidewall directly facing the second sidewall, and a fourth sidewall opposite to the third sidewall. A gap is formed between the second sidewall of the memory gate and the third sidewall of the control gate. A first single spacer structure is formed on the first sidewall of the memory gate and a second single spacer structure on the fourth sidewall of the control gate. A gap-filling layer is formed to fill up the gap.
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