公开(公告)号：US20200075397A1

公开(公告)日：2020-03-05

申请号：US16134982

申请日：2018-09-19

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Po-Chun Chen ,  Hsuan-Tung Chu ,  Yi-Wei Chen ,  Wei-Hsin Liu ,  Yu-Cheng Tung ,  Chia-Lung Chang

IPC: H01L21/762 ,  H01L21/02

Abstract: A method of forming an isolation structure includes the following steps. A substrate having a first trench, a second trench and a third trench is provided, wherein the opening of the third trench is larger than the opening of the second trench, and the opening of the second trench is larger than the opening of the first trench. A first oxide layer is formed to conformally cover the first trench, the second trench and the third trench by an atomic layer deposition (ALD) process. A second oxide layer fills up the first trench by an in-situ steam generation (ISSG) process.

公开(公告)号：US10535664B2

公开(公告)日：2020-01-14

申请号：US16012744

申请日：2018-06-19

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Po-Chun Chen ,  Wei-Hsin Liu ,  Chia-Lung Chang ,  Yi-Wei Chen ,  Han-Yung Tsai

IPC: H01L21/336 ,  H01L27/108 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/266 ,  H01L29/78

Abstract: A method of changing a formation rate of silicon oxide includes providing a substrate, wherein two conductive lines are disposed on the substrate and a recess is between the conductive lines. Later, a cleaning process is performed to clean the substrate and the conductive lines using diluted hydrofluoric acid. After the cleaning process, a silicon oxide layer is formed to cover a sidewall and a bottom of the recess, wherein a formation rate of the silicon oxide layer at the bottom of the recess is greater than a formation rate of the silicon oxide layer at the sidewall of the recess.

公开(公告)号：US20190363093A1

公开(公告)日：2019-11-28

申请号：US16012744

申请日：2018-06-19

Applicant: United Microelectronics Corp. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Po-Chun Chen ,  Wei-Hsin Liu ,  Chia-Lung Chang ,  Yi-Wei Chen ,  Han-Yung Tsai

IPC: H01L27/108 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L21/02

Abstract: A method of changing a formation rate of silicon oxide includes providing a substrate, wherein two conductive lines are disposed on the substrate and a recess is between the conductive lines. Later, a cleaning process is performed to clean the substrate and the conductive lines using diluted hydrofluoric acid. After the cleaning process, a silicon oxide layer is formed to cover a sidewall and a bottom of the recess, wherein a formation rate of the silicon oxide layer at the bottom of the recess is greater than a formation rate of the silicon oxide layer at the sidewall of the recess.

公开(公告)号：US10475900B2

公开(公告)日：2019-11-12

申请号：US15869005

申请日：2018-01-11

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Kai-Jiun Chang ,  Tsun-Min Cheng ,  Chih-Chieh Tsai ,  Jui-Min Lee ,  Yi-Wei Chen ,  Chia-Lung Chang ,  Wei-Hsin Liu

IPC: H01L29/49 ,  H01L21/285 ,  H01L29/66 ,  H01L27/108 ,  H01L21/28

Abstract: A method for manufacturing a semiconductor device with a cobalt silicide film is provided in the present invention. The method includes the steps of providing a silicon structure with an interlayer dielectric formed thereon, forming a contact hole in the interlayer dielectric to expose the silicon structure, depositing a cobalt film on the exposed silicon structure at a temperature between 300° C.-400° C., wherein a cobalt protecting film is in-situ formed on the surface of the cobalt film, performing a rapid thermal process to transform the cobalt film into a cobalt silicide film, and removing untransformed cobalt film.

公开(公告)号：US10262895B2

公开(公告)日：2019-04-16

申请号：US15859766

申请日：2018-01-02

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Mei-Ling Chen ,  Wei-Hsin Liu ,  Yi-Wei Chen ,  Chia-Lung Chang ,  Jui-Min Lee ,  Ching-Hsiang Chang ,  Tzu-Chin Wu ,  Shih-Fang Tzou

IPC: H01L21/02 ,  H01L21/768 ,  H01L27/108 ,  H01L21/8234 ,  H01L49/02

Abstract: The present invention provides a method for fabricating a semiconductor device, comprising at least the steps of: providing a substrate in which a memory region and a peripheral region are defined, the memory region includes a plurality of memory cells, each memory cell includes at least a first transistor and a capacitor, the peripheral region compress a second transistor, a first insulating layer is formed within the memory region and the peripheral region by an atomic layer deposition process, covering the capacitor of the memory cells in the memory region and the second transistor in the peripheral region, and a second insulating layer is formed, overlying the first insulating layer and the peripheral region. Finally, a contact structure is formed within the second insulating layer, and electrically connecting the second transistor.

公开(公告)号：US10224324B2

公开(公告)日：2019-03-05

申请号：US15681570

申请日：2017-08-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hsin Liu ,  Pi-Hsuan Lai

IPC: H01L27/02 ,  H01L27/11 ,  H01L21/033 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device is provided, including: a substrate having a first area and a second area; several first gate structures formed at the first area, and at least one of the first gate structures including a first hardmask on a first gate, and the first gate structure having a first gate length; several second gate structures formed at the second area, and at least one of the second gate structures including a second hardmask on a second gate, and the second gate structure having a second gate length. The first gate length is smaller than the second gate length, and the first hardmask contains at least a portion of nitrogen (N2)-based silicon nitride (SiN) which is free of OH concentration.

公开(公告)号：US20180361422A1

公开(公告)日：2018-12-20

申请号：US15939305

申请日：2018-03-29

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Jui-Min Lee ,  Ching-Hsiang Chang ,  Cheng-Hsu Huang ,  Yi-Wei Chen ,  Wei-Hsin Liu ,  Shih-Fang Tzou

IPC: B05D1/00 ,  B05C11/08 ,  H01L21/02 ,  H01L21/762

Abstract: A spin-on-dielectric process includes the following steps. A substrate is provided. A flowable material is spread on a surface of the substrate to forma spin-on-dielectric layer on the substrate, wherein the flowable material is heated to a temperature higher than 25° C.

公开(公告)号：US20180212034A1

公开(公告)日：2018-07-26

申请号：US15869005

申请日：2018-01-11

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Kai-Jiun Chang ,  Tsun-Min Cheng ,  Chih-Chieh Tsai ,  Jui-Min Lee ,  Yi-Wei Chen ,  Chia-Lung Chang ,  Wei-Hsin Liu

IPC: H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L21/285 ,  H01L27/108

Abstract: A method for manufacturing a semiconductor device with a cobalt silicide film is provided in the present invention. The method includes the steps of providing a silicon structure with an interlayer dielectric formed thereon, forming a contact hole in the interlayer dielectric to expose the silicon structure, depositing a cobalt film on the exposed silicon structure at a temperature between 300° C-400° C., wherein a cobalt protecting film is in-situ formed on the surface of the cobalt film, performing a rapid thermal process to transform the cobalt film into a cobalt silicide film, and removing untransformed cobalt film.

公开(公告)号：US20170309621A1

公开(公告)日：2017-10-26

申请号：US15136030

申请日：2016-04-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hsin Liu ,  Pi-Hsuan Lai

IPC: H01L27/088 ,  H01L21/033 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/11

CPC classification number: H01L27/088 ,  H01L21/0332 ,  H01L21/823456 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1116

Abstract: A semiconductor device is provided, including: a substrate having a first area and a second area; several first gate structures formed at the first area, and at least one of the first gate structures including a first hardmask on a first gate, and the first gate structure having a first gate length; several second gate structures formed at the second area, and at least one of the second gate structures including a second hardmask on a second gate, and the second gate structure having a second gate length. The first gate length is smaller than the second gate length, and the first hardmask contains at least a portion of nitrogen (N2)-based silicon nitride (SiN) which is free of OH concentration.

公开(公告)号：US09793267B1

公开(公告)日：2017-10-17

申请号：US15136030

申请日：2016-04-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hsin Liu ,  Pi-Hsuan Lai

IPC: H01L27/088 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/033 ,  H01L27/11

CPC classification number: H01L27/088 ,  H01L21/0332 ,  H01L21/823456 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1116

Abstract: A semiconductor device is provided, including: a substrate having a first area and a second area; several first gate structures formed at the first area, and at least one of the first gate structures including a first hardmask on a first gate, and the first gate structure having a first gate length; several second gate structures formed at the second area, and at least one of the second gate structures including a second hardmask on a second gate, and the second gate structure having a second gate length. The first gate length is smaller than the second gate length, and the first hardmask contains at least a portion of nitrogen (N2)-based silicon nitride (SiN) which is free of OH concentration.