公开(公告)号：US09627549B1

公开(公告)日：2017-04-18

申请号：US14874546

申请日：2015-10-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Biao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin ,  Su Xing ,  Tien-Yu Hsieh

IPC: H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L49/02 ,  H01L27/115 ,  H01L27/108

CPC classification number: H01L27/1052 ,  H01L27/108 ,  H01L27/115 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/66742 ,  H01L29/7869

Abstract: A semiconductor transistor device includes an oxide semiconductor layer having an active surface, a source electrode, a drain electrode, a gate electrode and a control capacitor. The gate electrode, the source electrode and the drain electrode are directly in contact with the active surface. The gate electrode is disposed between the drain electrode and the source electrode. The gate electrode, the source electrode and the drain electrode are separated from each other. The control capacitor is electrically connected to the gate electrode through a connection.

公开(公告)号：US09349873B1

公开(公告)日：2016-05-24

申请号：US14825511

申请日：2015-08-13

Applicant: United Microelectronics Corp.

Inventor： Zhi-Biao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin ,  Chun-Yuan Wu

IPC: H01L21/441 ,  H01L29/786 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L21/768 ,  H01L29/24

CPC classification number: H01L29/7869 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78648

Abstract: Provided is an oxide semiconductor device. A source, a drain, and a first gate are buried in a first dielectric layer, and the first gate is located between the source and the drain. A first barrier layer is located on the first dielectric layer, partially overlaps the source and the drain and overlaps the first gate. The first barrier layer includes a first opening and a second opening respectively corresponds to the source and the drain. An oxide semiconductor layer covers the first barrier layer and fills in the first opening and the second opening. A second barrier layer is located on the oxide semiconductor layer. A second gate is located on the second barrier layer and overlaps with the source, the drain, and the first gate.

Abstract translation: 提供一种氧化物半导体器件。 源极，漏极和第一栅极被埋在第一电介质层中，并且第一栅极位于源极和漏极之间。 第一阻挡层位于第一电介质层上，部分地与源极和漏极重叠并与第一栅极重叠。 第一阻挡层包括第一开口和第二开口，分别对应于源极和漏极。 氧化物半导体层覆盖第一阻挡层并填充在第一开口和第二开口中。 第二阻挡层位于氧化物半导体层上。 第二栅极位于第二阻挡层上并与源极，漏极和第一栅极重叠。