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37 条记录 (耗时 0.028 秒)

    Word line driver circuit with reduced leakage
    32.
    发明授权
    Word line driver circuit with reduced leakage 有权
    字线驱动电路漏电减少

    公开(公告)号：US07826301B2

    公开(公告)日：2010-11-02

    申请号：US12295745

    申请日：2007-08-28

    申请人： Dennis E. Dudeck ,  Donald Albert Evans ,  Hai Quang Pham ,  Wayne E. Werner ,  Ronald James Wozniak

    发明人： Dennis E. Dudeck ,  Donald Albert Evans ,  Hai Quang Pham ,  Wayne E. Werner ,  Ronald James Wozniak

    IPC分类号： G11C8/00

    CPC分类号： G11C8/08

    摘要： A word line driver circuit for use in a memory array including multiple memory cells and multiple word lines coupled to the memory cells for selectively accessing the memory cells includes a driver adapted to generate a word line signal as a function of a first set of address signals received by the word line driver circuit. The circuit further includes a switching circuit having a plurality of output nodes, the output nodes connected to respective ones of the plurality of word lines, and having an input node connected to an output of the driver and adapted to receive the word line signal. The switching circuit is operative to direct the word line signal to a selected one of the word lines during a memory access as a function of at least one control signal. Between a given pair of memory accesses, the output nodes and the input node of the switching circuit are held to a same prescribed voltage level to thereby substantially eliminate a leakage current path in the switching circuit.

    摘要翻译： 一种用于存储阵列的字线驱动电路，包括多个存储器单元和耦合到存储器单元的多个字线，用于选择性地访问存储器单元包括驱动器，其适于产生作为第一组地址信号的函数的字线信号 由字线驱动电路接收。 电路还包括具有多个输出节点的开关电路，输出节点连接到多个字线中的相应字线，并且具有连接到驱动器的输出并适于接收字线信号的输入节点。 切换电路可操作以作为至少一个控制信号的函数在存储器访问期间将字线信号引导到所选字线之一。 在给定的一对存储器访问之间，输出节点和开关电路的输入节点保持相同的规定电压电平，从而基本上消除了开关电路中的漏电流路径。

    Memory Circuit Having Reduced Power Consumption
    33.
    发明申请
    Memory Circuit Having Reduced Power Consumption 有权
    具有降低功耗的存储器电路

    公开(公告)号：US20100128549A1

    公开(公告)日：2010-05-27

    申请号：US12276576

    申请日：2008-11-24

    申请人： Dennis E. Dudeck ,  Donald Albert Evans ,  Hai Quang Pham ,  Wayne E. Werner ,  Ronald James Wozniak

    发明人： Dennis E. Dudeck ,  Donald Albert Evans ,  Hai Quang Pham ,  Wayne E. Werner ,  Ronald James Wozniak

    IPC分类号： G11C5/14 ,  G11C8/00

    CPC分类号： G11C5/147 ,  G11C8/12

    摘要： A memory circuit having reduced power consumption includes a plurality of memory sub-arrays and a shared circuit coupled to each of the memory sub-arrays. Each memory sub-array includes at least one row circuit, at least one column circuit, and a plurality of memory cells operatively coupled to the row and column circuits. The row and column circuits are operative to provide selective access to one or more of the memory cells. The shared circuit includes circuitry, external to the memory sub-arrays, which is operative to control one or more functions of the memory sub-arrays as a function of at least one control signal supplied to the memory circuit. The memory circuit is operative, with at least one of the memory sub-arrays operative, with one or more of the memory sub-arrays powered and concurrently with one or more of the memory sub-arrays unpowered.

    摘要翻译： 具有降低的功耗的存储器电路包括多个存储器子阵列和耦合到每个存储器子阵列的共享电路。 每个存储器子阵列包括至少一个行电路，至少一个列电路和可操作地耦合到行和列电路的多个存储单元。 行和列电路可操作以提供对一个或多个存储器单元的选择性访问。 共享电路包括存储器子阵列外部的电路，其可操作以根据提供给存储器电路的至少一个控制信号来控制存储器子阵列的一个或多个功能。 存储器电路是可操作的，其中存储器子阵列中的至少一个可操作，其中一个或多个存储器子阵列供电并与未被供电的一个或多个存储器子阵列同时发送。

    Memory cell for content-addressable memory
    34.
    发明授权
    Memory cell for content-addressable memory 有权
    用于内容寻址内存的内存单元

    公开(公告)号：US07558095B2

    公开(公告)日：2009-07-07

    申请号：US11743163

    申请日：2007-05-02

    申请人： Dennis E. Dudeck ,  Donald Albert Evans ,  Hai Quang Pham ,  Wayne E. Werner ,  Ronald James Wozniak

    发明人： Dennis E. Dudeck ,  Donald Albert Evans ,  Hai Quang Pham ,  Wayne E. Werner ,  Ronald James Wozniak

    IPC分类号： G11C15/00

    CPC分类号： G11C15/04 ,  Y10T29/49002

    摘要： A memory cell for use in a content-addressable memory comprises a first latch and a second latch. The first latch is operative to store a first bit associated with a first stored word, while the second latch is operative to store a second bit associated with a second stored word. The first and second latches collectively comprise a plurality of latch transistors. Each of the latch transistors comprises a respective channel. The channels of the latch transistors are oriented in substantially the same direction, resulting in a very compact memory cell implementation.

    摘要翻译： 用于内容寻址存储器的存储单元包括第一锁存器和第二锁存器。 第一锁存器用于存储与第一存储字相关联的第一位，而第二锁存器用于存储与第二存储字相关联的第二位。 第一和第二锁存器共同地包括多个锁存晶体管。 每个锁存晶体管包括相应的通道。 锁存晶体管的通道以大致相同的方向定向，导致非常紧凑的存储单元实现。

    Reduced Leakage Driver Circuit and Memory Device Employing Same
    35.
    发明申请
    Reduced Leakage Driver Circuit and Memory Device Employing Same 有权
    减少泄漏驱动电路和使用相同的存储器件

    公开(公告)号：US20090141580A1

    公开(公告)日：2009-06-04

    申请号：US11947210

    申请日：2007-11-29

    申请人： Donald Albert Evans ,  Richard J. McPartland ,  Hai Quang Pham ,  Wayne E. Werner ,  Ronald James Wozniak

    发明人： Donald Albert Evans ,  Richard J. McPartland ,  Hai Quang Pham ,  Wayne E. Werner ,  Ronald James Wozniak

    IPC分类号： G11C8/00

    CPC分类号： G11C8/08

    摘要： A row line driver circuit for use in a memory array including multiple memory cells and multiple row lines coupled to the memory cells for selectively accessing the memory cells includes an output stage adapted for connection to a corresponding one of the row lines and a control circuit connected to the output stage. The output stage is operative during an active phase of a given memory cycle to drive the corresponding row line to a potential as a function of at least one address signal received by the driver circuit. The control circuit is operative to generate at least one control signal for disabling the output stage at least during an inactive phase of the memory cycle to thereby substantially eliminate a leakage current path in the driver circuit.

    摘要翻译： 一种用于存储器阵列的行线驱动电路，包括多个存储器单元和耦合到存储器单元的多个行线，用于选择性地访问存储器单元包括适于连接到对应的一行行的输出级和连接到控制电路的控制电路 到输出阶段。 输出级在给定存储器周期的有效相位期间操作，以将对应的行线驱动为作为由驱动器电路接收的至少一个地址信号的函数的电位。 控制电路至少在存储器周期的非活动阶段期间产生至少一个禁止输出级的控制信号，从而基本上消除了驱动器电路中的漏电流路径。

    Accelerated Searching for Content-Addressable Memory
    36.
    发明申请
    Accelerated Searching for Content-Addressable Memory 有权
    加速搜索内容可寻址内存

    公开(公告)号：US20080025119A1

    公开(公告)日：2008-01-31

    申请号：US11460045

    申请日：2006-07-26

    申请人： Dennis E. Dudeck ,  Donald Albert Evans ,  Hai Quang Pham ,  Wayne E. Werner ,  Ronald James Wozniak

    发明人： Dennis E. Dudeck ,  Donald Albert Evans ,  Hai Quang Pham ,  Wayne E. Werner ,  Ronald James Wozniak

    IPC分类号： G11C7/02

    CPC分类号： G11C15/04 ,  G11C7/067

    摘要： A sensing circuit for use with a CAM circuit including multiple match lines and multiple CAM cells connected to the match lines includes at least one charge sharing circuit and at least one switching circuit connected to the charge sharing circuit. The switching circuit is operative to selectively connect the charge sharing circuit to a corresponding one of the match lines as a function of a first control signal supplied to the switching circuit. The sensing circuit further includes at least one comparator circuit connected to the corresponding match line and operative to generate an output signal indicative of a match between search data supplied to at least a given one of the CAM cells connected to the corresponding match line and data stored in the given CAM cell. The charge sharing circuit is operative to remove an amount of charge on the corresponding match line so as to reduce a voltage on the corresponding match line in conjunction with a search operation of the CAM cell.

    摘要翻译： 与包括多个匹配线的CAM电路一起使用的感测电路和连接到匹配线的多个CAM单元包括至少一个电荷共享电路和连接到电荷共享电路的至少一个开关电路。 开关电路用于根据提供给开关电路的第一控制信号选择性地将电荷共享电路连接到匹配线中的对应的一个。 感测电路还包括连接到对应匹配线的至少一个比较器电路，用于产生指示提供给连接到相应匹配线的至少一个给定的一个CAM单元的搜索数据和存储的数据之间的匹配的输出信号 在给定的CAM单元格中。 电荷共享电路用于去除相应匹配线上的电荷量，以便结合CAM单元的搜索操作来减小相应匹配线上的电压。

    Method and apparatus for reducing leakage current in a read only memory device using pre-charged sub-arrays
    37.
    发明授权
    Method and apparatus for reducing leakage current in a read only memory device using pre-charged sub-arrays 有权
    用于使用预充电子阵列在只读存储器件中减少泄漏电流的方法和装置

    公开(公告)号：US07042779B2

    公开(公告)日：2006-05-09

    申请号：US10764152

    申请日：2004-01-23

    申请人： Dennis E. Dudeck ,  Donald Albert Evans ,  Richard Joseph McPartland ,  Hai Quang Pham

    发明人： Dennis E. Dudeck ,  Donald Albert Evans ,  Richard Joseph McPartland ,  Hai Quang Pham

    IPC分类号： G11C7/00

    CPC分类号： G11C17/12 ,  G11C7/12

    摘要： A method and apparatus are provided for reducing leakage current in a read only memory device. Leakage current is reduced by precharging only a portion of the columns in a read only memory array during a given read cycle. The portion of the columns that are precharged is limited to a subset of columns that includes those columns that will be read during a given read cycle. A read column address is decoded to precharge only the portion of the columns of transistors that will be read during the given read cycle. The columns of transistors can be grouped into a plurality of sub-arrays and only those sub-arrays having columns that will be read during a given read cycle are precharged during the read cycle.

    摘要翻译： 提供了一种用于减少只读存储器件中的漏电流的方法和装置。 在给定的读取周期期间，通过在只读存储器阵列中只预先充电一部分列来减少泄漏电流。 预充电的列的部分被限制为包括在给定读周期期间将被读取的列的列的子集。 对读取列地址进行解码，以仅对在给定读取周期期间将被读取的晶体管列的部分进行预充电。 晶体管的列可以被分组成多个子阵列，并且仅在具有在给定读周期期间被读取的列的那些子阵列在读周期期间被预充电。