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1.发明授权Method and apparatus for reducing leakage current in a read only memory device using shortened precharge phase 有权使用缩短的预充电阶段来减少只读存储器件中的泄漏电流的方法和装置公开(公告)号：US07460424B2
公开(公告)日：2008-12-02
申请号：US11619344
申请日：2007-01-03
IPC分类号： G11C17/12
摘要： A method and apparatus are provided for reducing leakage current in a read only memory device. Leakage current is reduced by reducing the duration of the precharge cycle during each read cycle so that the associated leakage current will flow for a shorter time period during each cycle. The precharge phase is positioned at the beginning of each read cycle, prior to the evaluation phase. The precharge phase is terminated by a subsequent clock edge or by an internal time out prior to a subsequent clock edge. The time interval between when the columns reach their precharge voltage and the evaluation phase begins is reduced.
摘要翻译： 提供了一种用于减少只读存储器件中的漏电流的方法和装置。 通过在每个读取周期期间减少预充电周期的持续时间来降低泄漏电流，使得相关联的泄漏电流将在每个周期期间流动更短的时间段。 预充电阶段位于每个读取周期的开始之前，在评估阶段之前。 预充电阶段由后续时钟边沿或后续时钟边沿之前的内部超时终止。 列达到其预充电电压和评估阶段开始之间的时间间隔减小。
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2.发明授权Method and apparatus for reducing leakage current in a read only memory device using shortened precharge phase 有权使用缩短的预充电阶段来减少只读存储器件中的泄漏电流的方法和装置公开(公告)号：US07177212B2
公开(公告)日：2007-02-13
申请号：US10764150
申请日：2004-01-23
IPC分类号： G11C7/12
摘要： A method and apparatus are provided for reducing leakage current in a read only memory device. Leakage current is reduced by reducing the duration of the precharge cycle during each read cycle so that the associated leakage current will flow for a shorter time period during each cycle. The precharge phase is positioned at the beginning of each read cycle, prior to the evaluation phase. The precharge phase is terminated by a subsequent clock edge or by an internal time out prior to a subsequent clock edge. The time interval between when the columns reach their precharge voltage and the evaluation phase begins is reduced.
摘要翻译： 提供了一种用于减少只读存储器件中的漏电流的方法和装置。 通过在每个读取周期期间减少预充电周期的持续时间来降低泄漏电流，使得相关联的泄漏电流将在每个周期期间流动更短的时间段。 预充电阶段位于每个读取周期的开始之前，在评估阶段之前。 预充电阶段由后续时钟边沿或后续时钟边沿之前的内部超时终止。 列达到其预充电电压和评估阶段开始之间的时间间隔减小。
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3.发明授权Method and apparatus for reducing leakage current in a read only memory device using transistor bias 有权使用晶体管偏置在只读存储器件中减少泄漏电流的方法和装置公开(公告)号：US07085149B2
公开(公告)日：2006-08-01
申请号：US10764000
申请日：2004-01-23
申请人： Dennis E. Dudeck , Donald Albert Evans , Ross Alan Kohler , Richard Joseph McPartland , Hai Quang Pham
发明人： Dennis E. Dudeck , Donald Albert Evans , Ross Alan Kohler , Richard Joseph McPartland , Hai Quang Pham
IPC分类号： G11C17/08
摘要： A method and apparatus are provided for reducing leakage current in a read only memory device. Leakage current is reduced by applying a biased gate voltage (relative to a source voltage) to the gate of at least one of transistor in the array. The biased gate voltage is applied at least during a precharge phase of a read cycle. When the array transistors are n-channel transistors, the biased voltage is a negative bias voltage (relative to the source voltage). When the array transistors are p-channel transistors, the biased voltage is a positive bias voltage (relative to the source voltage). Applying a negative backgate bias to the transistor's p-well contact can also reduce n-channel transistor subthreshold leakage current. Thus, for an n-channel array, a negative gate voltage and backgate bias (optional) are applied to cell transistors in the off state. Similarly, the subthreshold leakage current of p-channel transistors is reduced by applying a more positive gate-to-source bias and a positive n-well-to-source bias.
摘要翻译： 提供了一种用于减少只读存储器件中的漏电流的方法和装置。 通过将偏置的栅极电压（相对于源极电压）施加到阵列中的至少一个晶体管的栅极来降低泄漏电流。 至少在读周期的预充电阶段期间施加偏置栅极电压。 当阵列晶体管是n沟道晶体管时，偏置电压是负偏置电压（相对于源极电压）。 当阵列晶体管是p沟道晶体管时，偏置电压是正偏置电压（相对于源极电压）。 对晶体管的p阱接触施加负的背栅极偏置还可以减少n沟道晶体管的亚阈值漏电流。 因此，对于n沟道阵列，负栅极电压和背栅极偏置（可选）被施加到处于断开状态的单元晶体管。 类似地，p沟道晶体管的亚阈值漏电流通过施加更正的栅极至源极偏压和正的n阱到源偏压来减小。
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4.发明授权Method and apparatus for reducing leakage current in a read only memory device using pre-charged sub-arrays 有权用于使用预充电子阵列在只读存储器件中减少泄漏电流的方法和装置公开(公告)号：US07042779B2
公开(公告)日：2006-05-09
申请号：US10764152
申请日：2004-01-23
IPC分类号： G11C7/00
摘要： A method and apparatus are provided for reducing leakage current in a read only memory device. Leakage current is reduced by precharging only a portion of the columns in a read only memory array during a given read cycle. The portion of the columns that are precharged is limited to a subset of columns that includes those columns that will be read during a given read cycle. A read column address is decoded to precharge only the portion of the columns of transistors that will be read during the given read cycle. The columns of transistors can be grouped into a plurality of sub-arrays and only those sub-arrays having columns that will be read during a given read cycle are precharged during the read cycle.
摘要翻译： 提供了一种用于减少只读存储器件中的漏电流的方法和装置。 在给定的读取周期期间，通过在只读存储器阵列中只预先充电一部分列来减少泄漏电流。 预充电的列的部分被限制为包括在给定读周期期间将被读取的列的列的子集。 对读取列地址进行解码，以仅对在给定读取周期期间将被读取的晶体管列的部分进行预充电。 晶体管的列可以被分组成多个子阵列，并且仅在具有在给定读周期期间被读取的列的那些子阵列在读周期期间被预充电。
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公开(公告)号：US06879509B2
公开(公告)日：2005-04-12
申请号：US10442832
申请日：2003-05-21
IPC分类号： G11C15/00 , G11C17/00 , G11C17/12 , H01L21/8246 , H01L27/112
CPC分类号： H01L27/112 , G11C17/12 , H01L27/11226
摘要： The present invention provides a read-only memory (ROM) architecture. An exemplary ROM array includes a plurality of columns, a plurality of rows, a first plurality of transistors or other switches representing a “0” data state or low voltage state, and a second plurality of transistors or other switches representing a “1” data state or high voltage state. Each transistor has a corresponding drain coupled to a column and a gate coupled to a row. Each transistor of the first plurality has a source coupled to a source voltage bus, and each transistor of the second plurality has a source not coupled to the source voltage bus, through use of a programmable contact window during fabrication. In various embodiments, for a selected column, drains of pair-wise adjacent transistors share a common drain-column contact and common diffusion region.
摘要翻译： 本发明提供一种只读存储器（ROM）架构。 示例性ROM阵列包括表示“0”数据状态或低电压状态的多个列，多行，第一多个晶体管或其他开关，以及表示“1”数据的第二多个晶体管或其他开关 状态或高电压状态。 每个晶体管具有耦合到列的相应漏极和耦合到一行的栅极。 第一多个晶体管的每个晶体管具有耦合到源极电压总线的源极，并且第二多个晶体管的每个晶体管通过在制造期间使用可编程接触窗口而具有未耦合到源极电压总线的源极。 在各种实施例中，对于所选择的列，成对相邻晶体管的漏极共享公共漏 - 列接触和公共扩散区。
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6.发明授权Method and apparatus for hot carrier programmed one time programmable (OTP) memory 有权用于热载波编程的一次可编程（OTP）存储器的方法和装置公开(公告)号：US07764541B2
公开(公告)日：2010-07-27
申请号：US10586176
申请日：2004-01-23
IPC分类号： G11C11/34
CPC分类号： G11C17/14 , H01L27/112
摘要： One time programmable memory devices are disclosed that are programmed using hot carrier induced degradation to alter one or more transistors characteristics. A one time programmable memory device is comprised of an array of transistors. Transistors in the array are selectively programmed using hot carrier induced changes in one or more transistor characteristics, such as changes to the saturation current, threshold voltage or both, of the transistors. The changes to the transistor characteristics are achieved in a similar manner to known hot carrier transistor aging principles. The disclosed one time programmable memory devices are small and programmable at low voltages and small current.
摘要翻译： 公开了一次可编程存储器件，其使用热载流子诱导劣化来编程以改变一个或多个晶体管特性。 一次可编程存储器件由晶体管阵列组成。 阵列中的晶体管使用热载流子引起的一个或多个晶体管特性的改变（例如晶体管的饱和电流，阈值电压或两者的改变）来选择性地编程。 以与已知的热载流子晶体管老化原理相似的方式实现晶体管特性的变化。 所公开的一次可编程存储器件小，可在低电压和小电流下编程。
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7.发明授权Non-volatile memory cell having channel initiated secondary electron injection programming mechanism 有权具有通道引发的二次电子注入编程机制的非易失性存储单元公开(公告)号：US06512700B1
公开(公告)日：2003-01-28
申请号：US09956646
申请日：2001-09-20
IPC分类号： G11C1604
CPC分类号： H01L29/42336 , G11C16/0416 , G11C2216/10 , H01L27/115 , H01L29/7885
摘要： A non-volatile memory cell and associated cell array and memory device having reduced program disturb, improved retention of programmed information, and reduced power consumption are disclosed. The memory cell includes a control device coupled to a switch device via a common floating gate, with the control device and the switch device formed on a common substrate, and the switch device formed at least in part in a tub region on the substrate. The tub region has a contact region formed therein. The contact region is adapted for application of a bias voltage to the tub region during a programming operation of the memory cell so as to reduce a programming voltage required to program the memory cell. In an illustrative embodiment, a drain-to-substrate voltage required to program the memory cell is reduced from a conventional value of about 6.5 volts to a value of about 3.5 volts, thus alleviating program disturb problems that can result, e.g., when the drain-to-substrate voltage is applied to multiple columns of an array of cells that are programmed one row at a time. The memory cell is programmed by channel initiated secondary electron (CHISEL) injection of charge onto the floating gate. The invention is particularly well suited for implementation in single-poly flash EEPROM embedded memory devices in integrated circuit applications.
摘要翻译： 公开了一种非易失性存储单元和相关联的单元阵列以及具有减少的程序干扰，改进的编程信息保留和降低的功耗的存储器件。 存储单元包括通过公共浮动栅极耦合到开关装置的控制装置，其中控制装置和开关装置形成在公共基板上，并且开关装置至少部分地形成在基板上的桶区域中。 桶区具有形成在其中的接触区域。 接触区域适于在存储单元的编程操作期间向桶区域施加偏置电压，以便减少编程存储单元所需的编程电压。 在说明性实施例中，对存储器单元编程所需的漏极到衬底的电压从约6.5伏特的常规值减小到约3.5伏特的值，从而减轻程序干扰问题，例如当漏极 对基板电压施加到一行一行编程的单元阵列的多列。 通过通道引发的二次电子（CHISEL）将电荷注入浮置栅极来对存储单元进行编程。 本发明特别适用于集成电路应用中的单聚焦闪存EEPROM嵌入式存储器件中的实现。
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公开(公告)号：US6104176A
公开(公告)日：2000-08-15
申请号：US69733
申请日：1998-04-30
CPC分类号： G05F3/24
摘要： The voltage regulator includes a regulator circuit, connected between a high potential and a low potential, regulating an output voltage based on an input voltage. The regulator circuit includes a changing circuit which changes at least one of a voltage range of the output voltage and a rate at which the output voltage changes with respect to changes in the input voltage. The changing circuit selectively increases a maximum value of the voltage range of the output voltage, and also selectively increases the rate at which the output voltage changes with respect to changes in the input voltage.
摘要翻译： 电压调节器包括连接在高电位和低电位之间的调节器电路，其基于输入电压调节输出电压。 调节器电路包括改变电路，其改变输出电压的电压范围和输出电压相对于输入电压的变化而变化的速率中的至少一个。 改变电路选择性地增加输出电压的电压范围的最大值，并且还选择性地增加输出电压相对于输入电压的变化而变化的速率。
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公开(公告)号：US6084804A
公开(公告)日：2000-07-04
申请号：US304888
申请日：1999-05-04
CPC分类号： G11C8/08
摘要： An integrated circuit memory array has a plurality of rows of memory cells, each row of memory cells being coupled to a respective row line for enabling the memory cells of the row. A row driver of the memory array provides a row voltage on the row line. A pull-up transistor of the row driver pulls up the row voltage in response to a row control signal. A parasitic diode of the pull-up transistor is coupled at its anode to the row line and is adapted to pull the row voltage down from a high state voltage to a diode drop voltage plus a low state voltage in response an enable block signal coupled to the cathode of the parasitic diode. A pull-down transistor of the row driver also pulls down the row voltage in response to the row control signal.
摘要翻译： 集成电路存储器阵列具有多行存储器单元，每行存储器单元耦合到相应的行线，以使能该行的存储单元。 存储器阵列的行驱动器在行线上提供行电压。 行驱动器的上拉晶体管响应于行控制信号而拉起行电压。 上拉晶体管的寄生二极管在其阳极处耦合到行线，并且适于将行电压从高状态电压降低到二极管压降电压加上低状态电压，以响应耦合到 寄生二极管的阴极。 行驱动器的下拉晶体管还响应于行控制信号而下拉行电压。
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公开(公告)号：US07254763B2
公开(公告)日：2007-08-07
申请号：US10931709
申请日：2004-09-01
IPC分类号： G01R31/28
CPC分类号： G06F11/1008 , G01R31/3187 , G11C29/42
摘要： A memory self-testing system, apparatus, and method are provided which allow for testing for a plurality of bit errors and passing memory arrays having an error level which is correctable using selected error correction coding. An exemplary system embodiment includes a memory array, a comparator, an integrator, and a test control circuit. The memory array is adapted to store input test data and output stored test data during a plurality of memory read and write test operations. The comparator compares the input test data and the stored test data for a plurality of bit positions, and provides a corresponding error signal when the stored test data is not identical to the input test data for each bit position of the plurality of bit positions. The integrator receives the corresponding error signal and maintains the corresponding error signal for each bit position during the plurality of test operations. The test control circuit provides a fail signal when a predetermined level of corresponding error signals have been provided for the plurality of bit positions.
摘要翻译： 提供了一种存储器自检系统，装置和方法，其允许测试多个位错误并且传递具有使用所选择的纠错编码可校正的误差级别的存储器阵列。 示例性系统实施例包括存储器阵列，比较器，积分器和测试控制电路。 存储器阵列适于在多个存储器读写测试操作期间存储输入测试数据并输出存储的测试数据。 比较器比较多个比特位置的输入测试数据和存储的测试数据，并且当存储的测试数据与多个比特位置的每个比特位置的输入测试数据不相同时，提供相应的误差信号。 在多个测试操作期间，积分器接收对应的误差信号并维持每个比特位置的对应误差信号。 当为多个位位置提供预定水平的对应误差信号时，测试控制电路提供故障信号。
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