公开(公告)号：US20110060433A1

公开(公告)日：2011-03-10

申请号：US12865831

申请日：2009-02-02

申请人： Xingdong Dai ,  Meghanad Wagh

发明人： Xingdong Dai ,  Meghanad Wagh

IPC分类号： G06F17/00

CPC分类号： G06F17/147 ,  G10L19/0212 ,  G10L19/16

摘要： Provided herein are hardware efficient bilinear algorithms and methods to compute MDCT/IMDCT of 2̂n and 4.3̂n points. The algorithms and methods for composite lengths have practical applications in MP3 audio encoding and decoding. The MDT/IMDCT can be converted to type-IV discrete cosine transforms (DCT-IV). Using group theory, the methods decomposes DCT-IV transform kernel matrix into groups of cyclic and Hankel product matrices. Bilinear algorithms are then applied to efficiently evaluate these groups. When implemented in VLSI, bilinear algorithms have improved the critical path delays over existing solutions. For MPEG-1/2 layer III (MP3) audio, proposed herein are several different versions of unified hardware architectures for both the short and long blocks and the forward and inverse transforms.

摘要翻译： 本文提供了硬件有效的双线性算法和方法来计算2n和4.3n点的MDCT / IMDCT。 复合长度的算法和方法在MP3音频编码和解码中具有实际应用。 MDT / IMDCT可以转换为IV型离散余弦变换（DCT-IV）。 利用群体理论，将DCT-IV变换核心矩阵分解为循环和汉克尔乘积矩阵。 然后应用双线性算法来有效地评估这些组。 当在VLSI中实现时，双线性算法已经改进了现有解决方案的关键路径延迟。 对于MPEG-1/2 Layer III（MP3）音频，本文提出了用于短块和长块以及正向和反向变换的统一硬件架构的几种不同版本。

公开(公告)号：US07593498B2

公开(公告)日：2009-09-22

申请号：US11541398

申请日：2006-09-29

申请人： Xingdong Dai ,  Vladimir Sindalovsky

发明人： Xingdong Dai ,  Vladimir Sindalovsky

IPC分类号： H04L7/00 ,  H04L25/00 ,  H04L25/40

CPC分类号： H04L25/0262 ,  H03K5/135 ,  H03M9/00 ,  H04J3/0685 ,  H04L7/0008

摘要： Methods and apparatus are provided for automatic rate identification and channel synchronization in a master-slave setting for high data throughput applications. An interface is provided for use between a parallel bus and a serial bus. The interface includes a plurality of serializer/deserializer circuits that generate a clock signal, wherein one of the serializer/deserializer circuits is a master circuit generating a master clock signal and the remaining of the serializer/deserializer circuits are slave circuits generating slave clock signals. The master clock signal is substantially phase-aligned to a reference clock and is distributed to the slave circuits. The interface also includes a clock divider associated with the master circuit for selectively generating a master clock signal having one or more lower data rates than the reference clock; and a frequency detector associated with each of the slave circuits for automatically detecting a rate of the master clock signal.

摘要翻译： 提供了用于高数据吞吐量应用的主从设置中的自动速率识别和信道同步的方法和装置。 提供了一种用于并行总线和串行总线之间的接口。 该接口包括产生时钟信号的多个串行器/解串行器电路，其中串行器/解串行电路之一是产生主时钟信号的主电路，串行器/解串行电路的其余部分是产生从时钟信号的从电路。 主时钟信号基本上与参考时钟相对准，并被分配给从属电路。 接口还包括与主电路相关联的时钟分频器，用于选择性地产生具有比参考时钟低一个或多个数据速率的主时钟信号; 以及与每个从属电路相关联的频率检测器，用于自动检测主时钟信号的速率。

公开(公告)号：US20080080600A1

公开(公告)日：2008-04-03

申请号：US11541398

申请日：2006-09-29

申请人： Xingdong Dai ,  Vladimir Sindalovsky

发明人： Xingdong Dai ,  Vladimir Sindalovsky

IPC分类号： H04L5/16 ,  H04L7/00

CPC分类号： H04L25/0262 ,  H03K5/135 ,  H03M9/00 ,  H04J3/0685 ,  H04L7/0008

摘要： Methods and apparatus are provided for automatic rate identification and channel synchronization in a master-slave setting for high data throughput applications. An interface is provided for use between a parallel bus and a serial bus. The interface includes a plurality of serializer/deserializer circuits that generate a clock signal, wherein one of the serializer/deserializer circuits is a master circuit generating a master clock signal and the remaining of the serializer/deserializer circuits are slave circuits generating slave clock signals. The master clock signal is substantially phase-aligned to a reference clock and is distributed to the slave circuits. The interface also includes a clock divider associated with the master circuit for selectively generating a master clock signal having one or more lower data rates than the reference clock; and a frequency detector associated with each of the slave circuits for automatically detecting a rate of the master clock signal.

摘要翻译： 提供了用于高数据吞吐量应用的主从设置中的自动速率识别和信道同步的方法和装置。 提供了一种用于并行总线和串行总线之间的接口。 该接口包括产生时钟信号的多个串行器/解串行器电路，其中串行器/解串行电路之一是产生主时钟信号的主电路，串行器/解串行电路的其余部分是产生从时钟信号的从电路。 主时钟信号基本上与参考时钟相对准，并被分配给从属电路。 该接口还包括与主电路相关联的时钟分频器，用于选择性地产生具有比参考时钟低一个或多个数据速率的主时钟信号; 以及与每个从属电路相关联的频率检测器，用于自动检测主时钟信号的速率。

公开(公告)号：US07995695B2

公开(公告)日：2011-08-09

申请号：US11969440

申请日：2008-01-04

申请人： Yasser Ahmed ,  Xingdong Dai ,  Vladimir Sindalovsky ,  Lane Smith

发明人： Yasser Ahmed ,  Xingdong Dai ,  Vladimir Sindalovsky ,  Lane Smith

IPC分类号： H04L7/00 ,  H04L25/00 ,  H04L25/40

CPC分类号： H03M9/00 ,  H04L7/005 ,  H04L7/04

摘要： In an exemplary embodiment, a data alignment system comprises a First-In First-Out register (FIFO), a programmable pattern generator connected to the FIFO, and a controller connected to the programmable pattern generator and the FIFO. The FIFO is configured to provide data to or receive data from a first data lane of a serial data link having one or more lanes. Each data lane of the serial data link is configured to transmit a respective serial data stream. The programmable pattern generator is configured to generate a plurality of alignment symbols. The controller is configured to manage the alignment of the one or more data lanes of the serial data link and the insertion of a selected one of the plurality of alignment symbols into each of the serial data streams.

摘要翻译： 在示例性实施例中，数据对准系统包括先进先出寄存器（FIFO），连接到FIFO的可编程模式发生器和连接到可编程模式发生器和FIFO的控制器。 FIFO被配置为向具有一个或多个通道的串行数据链路的第一数据通道提供数据或从其接收数据。 串行数据链路的每个数据通道被配置为发送相应的串行数据流。 可编程模式发生器被配置为生成多个对准符号。 控制器被配置为管理串行数据链路的一个或多个数据通道的对准以及将多个对准符号中选择的一个对准符号插入到每个串行数据流中。