公开(公告)号：US20080127003A1

公开(公告)日：2008-05-29

申请号：US12010136

申请日：2008-01-22

Applicant: Yow-Tyng Nieh ,  Sheng-Yu Hsu ,  Shih-Hsu Huang ,  Yeong-Jar Chang

Inventor： Yow-Tyng Nieh ,  Sheng-Yu Hsu ,  Shih-Hsu Huang ,  Yeong-Jar Chang

IPC: G06F17/50

CPC classification number: G06F1/10

Abstract: We propose an opposite-phase scheme for peak current reduction. The basic idea is to divide the clock buffers at each level of the clock tree into two sets: one half of the clock buffers operate at the same phase as the clock source, and the other half of the clock buffers operate at the opposite phase to the clock source. Consequently, our approach can effectively reduce the peak current of the clock tree. The method enables the opposite-phase scheme to combine with the electronic design automation (EDA) tools that are commonly used in modern industries.

Abstract translation: 我们提出了用于峰值电流降低的反相方案。 基本思想是将时钟树的每个级别的时钟缓冲区分为两组：一半时钟缓冲器与时钟源工作在相同的相位，而另一半的时钟缓冲器工作在相反的阶段 时钟源。 因此，我们的方法可以有效地降低时钟树的峰值电流。 该方法使得相反方案能够与现代工业中常用的电子设计自动化（EDA）工具相结合。

公开(公告)号：US20080125990A1

公开(公告)日：2008-05-29

申请号：US11563253

申请日：2006-11-27

Applicant: Yeong-Jar Chang

Inventor： Yeong-Jar Chang

IPC: G06F19/00 ,  G06F11/25 ,  G06F11/27 ,  G01R29/26

CPC classification number: G06F11/24 ,  G01R31/3167

Abstract: A BIST circuit for testing both an analog-to-digital converter and a phase lock loop includes a controllable delay circuit, a NAND gate, a dividing circuit, a NOR gate and a charge/discharge circuit. The invention reduces the period of the signal under test, converts its pulse width to voltage and measures the output via an ADC. The clock jitter becomes sensitive through a delay cancellation method, thus, the accuracy is improved. The invention further comprises all testing procedure for period jitters of a PLL and static characteristics of an ADC. The test error caused by process variation can be corrected by a controllable delay circuit such that the error determination of the test result is prevented.

Abstract translation: 用于测试模数转换器和锁相环的BIST电路包括可控延迟电路，NAND门，分频电路，NOR门和充电/放电电路。 本发明减少被测信号的周期，将其脉冲宽度转换为电压，并通过ADC测量输出。 时钟抖动通过延迟消除方法变得敏感，因此提高了精度。 本发明还包括用于PLL的周期抖动和ADC的静态特性的所有测试程序。 可以通过可控延迟电路校正由过程变化引起的测试误差，从而防止测试结果的错误确定。

公开(公告)号：US07319625B2

公开(公告)日：2008-01-15

申请号：US11481966

申请日：2006-07-07

Applicant: Yeong-Jar Chang ,  Kun-Lun Luo ,  Jung-Chi Ho ,  Cheng-Wen Wu ,  Chin-Jung Su

Inventor： Yeong-Jar Chang ,  Kun-Lun Luo ,  Jung-Chi Ho ,  Cheng-Wen Wu ,  Chin-Jung Su

IPC: G11C7/00

CPC classification number: G11C29/12 ,  G11C29/12005 ,  G11C29/50 ,  G11C2029/5006

Abstract: A built-in memory current test circuit to test a memory on a chip is disclosed, comprising a built-in self-test circuit and a dynamic current generation module. The built-in self-test circuit is disposed on the chip to receive and process a test signal and generate a control signal to control operation of the memory and a current control code. The dynamic current generation module, also disposed on the chip, produces a test current into the memory based on the current control code. The current switch time is reduced in the built-in memory current test circuit, and an integrated test combining functional and stress tests can thus be performed.

Abstract translation: 公开了一种用于测试芯片上的存储器的内置存储器电流测试电路，其包括内置的自测电路和动态电流产生模块。 内置自检电路设置在芯片上，以接收和处理测试信号，并产生控制信号以控制存储器的操作和电流控制代码。 也设置在芯片上的动态电流产生模块基于当前控制码产生到存储器中的测试电流。 内置存储器电流测试电路中的当前切换时间减少，因此可以执行组合功能和应力测试的集成测试。