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    Opposite-phase scheme for peak current reduction
    2.
    发明申请
    Opposite-phase scheme for peak current reduction 有权
    峰值电流降低的相位方案

    公开(公告)号：US20070040596A1

    公开(公告)日：2007-02-22

    申请号：US11285007

    申请日：2005-11-23

    申请人： Yow-Tyng Nieh ,  Sheng-Yu Hsu ,  Shih-Hsu Huang ,  Yeong-Jar Chang

    发明人： Yow-Tyng Nieh ,  Sheng-Yu Hsu ,  Shih-Hsu Huang ,  Yeong-Jar Chang

    IPC分类号： G06F1/04

    CPC分类号： G06F1/10

    摘要： We propose an opposite-phase scheme for peak current reduction. The basic idea is to divide the clock buffers at each level of the clock tree into two sets: one half of the clock buffers operate at the same phase as the clock source, and the other half of the clock buffers operate at the opposite phase to the clock source. Consequently, our approach can effectively reduce the peak current of the clock tree. The method enables the opposite-phase scheme to combine with the electronic design automation (EDA) tools that are commonly used in modern industries.

    摘要翻译： 我们提出了用于峰值电流降低的反相方案。 基本思想是将时钟树的每个级别的时钟缓冲区分为两组：一半时钟缓冲器与时钟源工作在相同的相位，而另一半的时钟缓冲器工作在相反的阶段 时钟源。 因此，我们的方法可以有效地降低时钟树的峰值电流。 该方法使得相反方案能够与现代工业中常用的电子设计自动化（EDA）工具相结合。

    Opposite-phase scheme for peak current reduction
    3.
    发明授权
    Opposite-phase scheme for peak current reduction 有权
    峰值电流降低的相位方案

    公开(公告)号：US07904874B2

    公开(公告)日：2011-03-08

    申请号：US12010136

    申请日：2008-01-22

    申请人： Yow-Tyng Nieh ,  Sheng-Yu Hsu ,  Shih-Hsu Huang ,  Yeong-Jar Chang

    发明人： Yow-Tyng Nieh ,  Sheng-Yu Hsu ,  Shih-Hsu Huang ,  Yeong-Jar Chang

    IPC分类号： G06F17/50

    CPC分类号： G06F1/10

    摘要： We propose an opposite-phase scheme for peak current reduction. The basic idea is to divide the clock buffers at each level of the clock tree into two sets: one half of the clock buffers operate at the same phase as the clock source, and the other half of the clock buffers operate at the opposite phase to the clock source. Consequently, our approach can effectively reduce the peak current of the clock tree. The method enables the opposite-phase scheme to combine with the electronic design automation (EDA) tools that are commonly used in modern industries.

    摘要翻译： 我们提出了用于峰值电流降低的反相方案。 基本思想是将时钟树的每个级别的时钟缓冲区分为两组：一半时钟缓冲器与时钟源工作在相同的相位，而另一半的时钟缓冲器工作在相反的阶段 时钟源。 因此，我们的方法可以有效地降低时钟树的峰值电流。 该方法使得相反方案能够与现代工业中常用的电子设计自动化（EDA）工具相结合。

    Opposite-phase scheme for peak current reduction
    4.
    发明申请
    Opposite-phase scheme for peak current reduction 有权
    峰值电流降低的相位方案

    公开(公告)号：US20080127003A1

    公开(公告)日：2008-05-29

    申请号：US12010136

    申请日：2008-01-22

    申请人： Yow-Tyng Nieh ,  Sheng-Yu Hsu ,  Shih-Hsu Huang ,  Yeong-Jar Chang

    发明人： Yow-Tyng Nieh ,  Sheng-Yu Hsu ,  Shih-Hsu Huang ,  Yeong-Jar Chang

    IPC分类号： G06F17/50

    CPC分类号： G06F1/10

    摘要： We propose an opposite-phase scheme for peak current reduction. The basic idea is to divide the clock buffers at each level of the clock tree into two sets: one half of the clock buffers operate at the same phase as the clock source, and the other half of the clock buffers operate at the opposite phase to the clock source. Consequently, our approach can effectively reduce the peak current of the clock tree. The method enables the opposite-phase scheme to combine with the electronic design automation (EDA) tools that are commonly used in modern industries.

    摘要翻译： 我们提出了用于峰值电流降低的反相方案。 基本思想是将时钟树的每个级别的时钟缓冲区分为两组：一半时钟缓冲器与时钟源工作在相同的相位，而另一半的时钟缓冲器工作在相反的阶段 时钟源。 因此，我们的方法可以有效地降低时钟树的峰值电流。 该方法使得相反方案能够与现代工业中常用的电子设计自动化（EDA）工具相结合。