公开(公告)号：US07945404B2

公开(公告)日：2011-05-17

申请号：US12108796

申请日：2008-04-24

Applicant: Jung-Chi Ho ,  Sheng-Bin Lin ,  Yeong-Jar Chang

Inventor： Jung-Chi Ho ,  Sheng-Bin Lin ,  Yeong-Jar Chang

IPC: G01R23/00 ,  G06F19/00

CPC classification number: G01R29/26 ,  G01R31/3016 ,  G01R31/31709

Abstract: Provided is a measurement circuit for measuring a jitter of a clock signal. Delay elements delay the clock signal into delayed clock signal. Latches latch the delayed clock signals to indicate whether transition edges of the clock signal is within a window value which is corresponding to delays of the delay elements. Based on the latch result from the latches, a finite state machine generates control signals for controlling the delay elements. If the latch result indicates that the transition edges of the clock signal is not within the window value, the control signals adjust the delays of the delay elements and the window value. The jitter of the clock signal is measured based on the delays of the delay elements and the window value.

Abstract translation: 提供了一种用于测量时钟信号的抖动的测量电路。 延迟元件将时钟信号延迟到延迟的时钟信号。 锁存器锁存延迟的时钟信号以指示时钟信号的转换边沿是否在对应于延迟元件的延迟的窗口值内。 基于锁存器的锁存结果，有限状态机产生用于控制延迟元件的控制信号。 如果锁存结果指示时钟信号的转换边缘不在窗口值内，则控制信号调整延迟元件的延迟和窗口值。 基于延迟元件的延迟和窗口值来测量时钟信号的抖动。

公开(公告)号：US07912166B2

公开(公告)日：2011-03-22

申请号：US11870113

申请日：2007-10-10

Applicant: Jen-Chien Hsu ,  Hung-Wen Lu ,  Chau-Chin Su ,  Yeong-Jar Chang

Inventor： Jen-Chien Hsu ,  Hung-Wen Lu ,  Chau-Chin Su ,  Yeong-Jar Chang

IPC: H04L7/00

CPC classification number: G01R29/26 ,  G01R31/31709

Abstract: A jitter measurement circuit and a method for calibrating the jitter measurement circuit are disclosed. The jitter measurement circuit includes a synchronous dual-phase detector and a decision circuit. In a test mode, a probability distribution function (PDF) of the jitter of a clock signal output by a circuit under test is obtained. In a calibration mode, a random clock, which is externally generated or generated by a free-run oscillator in the circuit under test, is used to calibrate the synchronous dual-phase detector. The decision circuit performs logic operations, data latching and counting on a phase relationship detected by the synchronous dual-phase detector in order to obtain a counting value and a PDF relative to the jitter of the clock signal.

Abstract translation: 公开了抖动测量电路和校准抖动测量电路的方法。 抖动测量电路包括同步双相检测器和判定电路。 在测试模式中，获得由被测电路输出的时钟信号的抖动的概率分布函数（PDF）。 在校准模式中，由被测电路中的自由振荡器外部产生或产生的随机时钟用于校准同步双相检测器。 决定电路对由同步双相检测器检测的相位关系进行逻辑运算，数据锁存和计数，以获得相对于时钟信号的抖动的计数值和PDF。

公开(公告)号：US07716542B2

公开(公告)日：2010-05-11

申请号：US11939282

申请日：2007-11-13

Applicant: Yeong-Jar Chang ,  Chung-Fu Lin

Inventor： Yeong-Jar Chang ,  Chung-Fu Lin

IPC: G01R31/28 ,  G11C29/00 ,  G06F11/00

CPC classification number: G11C29/16 ,  G01R31/318552 ,  G06F11/2215 ,  G11C29/12015 ,  G11C29/14

Abstract: A programmable memory built-in self-test circuit and a clock switching circuit thereof are provided. The memory built-in self-test circuit is able to provide more self-test functions preset by a user, simplify the redundant circuit in the prior art and reduce chip area and lower the cost by means of an instruction decoder and a built-in self-test controller. The present invention also provides some peripheral control circuits of a memory. The control circuits occupies less area and enables the memory to be tested more flexibly. The present invention further provides a clock switching circuit enabling a chip to be correctly tested under different clock speeds, which benefits to advance the testability and the analyzability of the memory embedded in a chip and thereby increase fault coverage.

Abstract translation: 提供了可编程存储器内置自检电路及其时钟切换电路。 存储器内置的自检电路能够提供用户预设的更多的自检功能，简化了现有技术中的冗余电路，并借助于指令解码器和内置功能降低了芯片面积并降低了成本 自检控制器。 本发明还提供了一些存储器的外围控制电路。 控制电路占用的面积较小，能够更灵活地测试存储器。 本发明还提供一种能够在不同时钟速度下正确测试芯片的时钟切换电路，这有利于提高嵌入在芯片中的存储器的可测试性和可分析性，从而增加故障覆盖。

公开(公告)号：US07352212B2

公开(公告)日：2008-04-01

申请号：US11285007

申请日：2005-11-23

Applicant: Yow-Tyng Nieh ,  Sheng-Yu Hsu ,  Shih-Hsu Huang ,  Yeong-Jar Chang

Inventor： Yow-Tyng Nieh ,  Sheng-Yu Hsu ,  Shih-Hsu Huang ,  Yeong-Jar Chang

IPC: H03K19/00

CPC classification number: G06F1/10

Abstract: We propose an opposite-phase scheme for peak current reduction. The basic idea is to divide the clock buffers at each level of the clock tree into two sets: one half of the clock buffers operate at the same phase as the clock source, and the other half of the clock buffers operate at the opposite phase to the clock source. Consequently, our approach can effectively reduce the peak current of the clock tree. The method enables the opposite-phase scheme to combine with the electronic design automation (EDA) tools that are commonly used in modern industries.

公开(公告)号：US20070153597A1

公开(公告)日：2007-07-05

申请号：US11481966

申请日：2006-07-07

Applicant: Yeong-Jar Chang ,  Kun-Lun Luo ,  Jung-Chi Ho ,  Cheng-Wen Wu ,  Chin-Jung Su

Inventor： Yeong-Jar Chang ,  Kun-Lun Luo ,  Jung-Chi Ho ,  Cheng-Wen Wu ,  Chin-Jung Su

IPC: G11C29/00 ,  G11C7/00

CPC classification number: G11C29/12 ,  G11C29/12005 ,  G11C29/50 ,  G11C2029/5006

Abstract: A built-in memory current test circuit to test a memory on a chip is disclosed, comprising a built-in self-test circuit and a dynamic current generation module. The built-in self-test circuit is disposed on the chip to receive and process a test signal and generate a control signal to control operation of the memory and a current control code. The dynamic current generation module, also disposed on the chip, produces a test current into the memory based on the current control code. The current switch time is reduced in the built-in memory current test circuit, and an integrated test combining functional and stress tests can thus be performed.

Abstract translation: 公开了一种用于测试芯片上的存储器的内置存储器电流测试电路，其包括内置的自测电路和动态电流产生模块。 内置自检电路设置在芯片上，以接收和处理测试信号，并产生控制信号以控制存储器的操作和电流控制代码。 也设置在芯片上的动态电流产生模块基于当前控制码产生到存储器中的测试电流。 内置存储器电流测试电路中的当前切换时间减少，因此可以执行组合功能和应力测试的集成测试。

公开(公告)号：US20060156104A1

公开(公告)日：2006-07-13

申请号：US11140745

申请日：2005-06-01

Applicant: Yeong-Jar Chang ,  Wen-Ching Wu ,  Kun-Lun Luo ,  Chia-Jen Lee

Inventor： Yeong-Jar Chang ,  Wen-Ching Wu ,  Kun-Lun Luo ,  Chia-Jen Lee

IPC: G01R31/28

CPC classification number: G01R31/318555

Abstract: A wrapper testing circuit and method thereof for System-On-a-Chip is provided for electrical tests of core circuits of an integrated circuit. The testing circuit includes a decoding logic with an encoding table for receiving test signals and delivering control signals in response to the test signals according to the table; a plurality of registers for saving the control signals temporarily and delivering the control signals to the core circuits; a bypass circuit for delivering the test signals; and an instruction register for saving the test signals temporarily and refreshing the data in the registers and the bypass circuits after the decoding logic issues the control signals. The encoding of the control signals is completed in one period. Compared with the serial encoding in the prior art, test time is reduced.

Abstract translation: 提供了一种用于片上系统的封装测试电路及其方法，用于集成电路的核心电路的电气测试。 测试电路包括具有编码表的解码逻辑，用于接收测试信号并根据该表响应于测试信号传递控制信号; 多个寄存器，用于暂时保存控制信号并将控制信号传送到核心电路; 用于传递测试信号的旁路电路; 以及在解码逻辑发出控制信号之后暂时保存测试信号并刷新寄存器和旁路电路中的数据的指令寄存器。 控制信号的编码在一个周期内完成。 与现有技术的串行编码相比，测试时间缩短。

公开(公告)号：US06950046B2

公开(公告)日：2005-09-27

申请号：US10894054

申请日：2004-07-20

Applicant: Pei-Wen Luo ,  Yeong-Jar Chang ,  Jung-Chi Ho ,  Wen-Ching Wu

Inventor： Pei-Wen Luo ,  Yeong-Jar Chang ,  Jung-Chi Ho ,  Wen-Ching Wu

IPC: G01R31/28 ,  H03M1/10 ,  H03M3/00

CPC classification number: H03M3/378 ,  H03M3/458

Abstract: IC with built-in self-test and design method thereof. The IC comprises an SD-ADC and a Dft circuit. The Dft circuit uses a digital stimulus signal to solve the deadlock problem of the on-chip analog testing and avoid thermal noise. Moreover, according to the design method of the IC, circuits having different specification can use the Dft circuit without performance degradation for original SD-ADC.

Abstract translation: IC内置自检及其设计方法。 IC包括SD-ADC和Dft电路。 Dft电路使用数字刺激信号来解决片上模拟测试的死锁问题，并避免热噪声。 此外，根据IC的设计方法，具有不同规格的电路可以使用Dft电路，而不会对原始SD-ADC造成性能下降。

公开(公告)号：US20120138961A1

公开(公告)日：2012-06-07

申请号：US12961512

申请日：2010-12-07

Applicant: Po-Yao Huang ,  Chia-Yu Jin ,  Yeong-Jar Chang

Inventor： Po-Yao Huang ,  Chia-Yu Jin ,  Yeong-Jar Chang

IPC: H01L31/12 ,  H01L31/18

CPC classification number: G02B6/4292 ,  G02B6/4214 ,  G02B6/4249 ,  G02B6/4251 ,  G02B6/4253 ,  G02B6/4257 ,  G02B6/4274 ,  G02B6/428 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package structure includes a package substrate, at least a chip, solder balls, a light emitting/receiving device, a optical intermediary device and an optical transmission device. The package substrate has a first surface, a second surface, a circuit and solder ball pads, wherein each solder ball pad is electrically connected to the circuit. The chip is disposed on the first surface and electrically connected to the circuit. The solder balls are respectively disposed on the solder ball pads. The light emitting/receiving device is disposed on the package substrate and electrically connected to the circuit. The optical intermediary device is disposed above the light emitting/receiving device. The optical transmission device is inserted in the optical intermediary device, wherein a light emitting by the light emitting/receiving device is emitted to the optical transmission device via the optical intermediary device so that an optical signal is transmitted through the optical transmission device.

Abstract translation: 半导体封装结构包括封装衬底，至少芯片，焊球，发光/接收器件，光中介器件和光传输器件。 封装衬底具有第一表面，第二表面，电路和焊球垫，其中每个焊球焊盘电连接到电路。 芯片设置在第一表面上并电连接到电路。 焊球分别设置在焊球垫上。 发光/接收装置设置在封装基板上并与电路电连接。 光中继装置设置在发光/接收装置的上方。 光传输装置被插入到光中继装置中，其中由发光/接收装置发射的光经由光中介装置发射到光传输装置，使得光信号通过光传输装置传输。

公开(公告)号：US20100031206A1

公开(公告)日：2010-02-04

申请号：US12512086

申请日：2009-07-30

Applicant: Chang-Chung Wu ,  Chi-Che Chen ,  Jung-Chi Ho ,  Woei-Tzy Jong ,  Yeong-Jar Chang

Inventor： Chang-Chung Wu ,  Chi-Che Chen ,  Jung-Chi Ho ,  Woei-Tzy Jong ,  Yeong-Jar Chang

IPC: G06F17/50

CPC classification number: G06F17/5063

Abstract: Method and technique for analogue circuit synthesis. An analogue circuit usually includes many circuit components, and characteristics and functions of each circuit component are controlled by many corresponding parameters. In the presented invention, selected key design parameters of selected critical circuit components, as well as optimization targets, design specification or/and design constraint, are transformed into an optimization plan, and an optimization engine iterates circuit level or system level numerical simulations by changing values of the selected key design parameters recorded in the optimization plan, so as to find optimized parameters and circuit components which allow the analogue circuit to match the design specification/constraint and to approach the optimization target. Thus a systematic automation for analogue circuit synthesis/design/optimization is achieved.

Abstract translation: 模拟电路合成的方法和技术。 模拟电路通常包括许多电路元件，并且每个电路元件的特性和功能由许多相应的参数控制。 在本发明中，所选择的关键电路组件的选择的关键设计参数以及优化目标，设计规范或/和设计约束被转换成优化计划，优化引擎通过改变电路级或系统级数值模拟来迭代 所选择的关键设计参数的值被记录在优化计划中，以便找到允许模拟电路匹配设计规范/约束并且接近优化目标的优化参数和电路组件。 因此，实现了模拟电路合成/设计/优化的系统自动化。

公开(公告)号：US07603602B2

公开(公告)日：2009-10-13

申请号：US11563253

申请日：2006-11-27

Applicant: Yeong-Jar Chang

Inventor： Yeong-Jar Chang

IPC: G01R31/28 ,  H03M1/10

CPC classification number: G06F11/24 ,  G01R31/3167

Abstract: A BIST circuit for testing both an analog-to-digital converter and a phase lock loop includes a controllable delay circuit, a NAND gate, a dividing circuit, a NOR gate and a charge/discharge circuit. The invention reduces the period of the signal under test, converts its pulse width to voltage and measures the output via an ADC. The clock jitter becomes sensitive through a delay cancellation method, thus, the accuracy is improved. The invention further comprises all testing procedure for period jitters of a PLL and static characteristics of an ADC. The test error caused by process variation can be corrected by a controllable delay circuit such that the error determination of the test result is prevented.

Abstract translation: 用于测试模数转换器和锁相环的BIST电路包括可控延迟电路，NAND门，分频电路，NOR门和充电/放电电路。 本发明减少被测信号的周期，将其脉冲宽度转换为电压，并通过ADC测量输出。 时钟抖动通过延迟消除方法变得敏感，因此提高了精度。 本发明还包括用于PLL的周期抖动和ADC的静态特性的所有测试程序。 可以通过可控延迟电路校正由过程变化引起的测试误差，从而防止测试结果的错误确定。