公开(公告)号：US07700452B2

公开(公告)日：2010-04-20

申请号：US11847083

申请日：2007-08-29

申请人： Ming-Hua Yu ,  Tai-Chun Huang

发明人： Ming-Hua Yu ,  Tai-Chun Huang

IPC分类号： H01L29/78

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833

摘要： A semiconductor device, such as a PMOS or an NMOS transistor, having a stressed channel region is provided. The semiconductor device is formed by recessing the source/drain regions after forming a gate stack. The substrate is removed under the gate stack. Thereafter, an epitaxial layer is formed under the gate stack and in the source/drain regions. The epitaxial layer may be doped in the source/drain regions. In an embodiment, a lower portion of the epitaxial layer and the epitaxial layer under the gate stack may be doped with a conductivity type opposite of the conductivity type of the source/drain regions. In another embodiment of the present invention, a lower portion of the epitaxial layer is left undoped.

摘要翻译： 提供具有应力通道区域的诸如PMOS或NMOS晶体管的半导体器件。 半导体器件通过在形成栅极堆叠之后使源极/漏极区域凹陷来形成。 在栅极堆叠下去除衬底。 此后，在栅叠层和源极/漏极区内形成外延层。 外延层可以掺杂在源极/漏极区域中。 在一个实施例中，外延层的下部和栅叠层下的外延层可以掺杂有与源极/漏极区的导电类型相反的导电类型。 在本发明的另一实施例中，外延层的下部未被掺杂。

公开(公告)号：US20080246057A1

公开(公告)日：2008-10-09

申请号：US11732889

申请日：2007-04-05

申请人： Hsien-Hsin Lin ,  Weng Chang ,  Chien-Chang Su ,  Kuan-Yu Chen ,  Hsueh-Chang Sung ,  Ming-Hua Yu

发明人： Hsien-Hsin Lin ,  Weng Chang ,  Chien-Chang Su ,  Kuan-Yu Chen ,  Hsueh-Chang Sung ,  Ming-Hua Yu

IPC分类号： H01L29/78

CPC分类号： H01L29/66477 ,  H01L21/02532 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A composite semiconductor structure and method of forming the same are provided. The composite semiconductor structure includes a first silicon-containing compound layer comprising an element selected from the group consisting essentially of germanium and carbon; a silicon layer on the first silicon-containing compound layer, wherein the silicon layer comprises substantially pure silicon; and a second silicon-containing compound layer comprising the element on the silicon layer. The first and the second silicon-containing compound layers have substantially lower silicon concentrations than the silicon layer. The composite semiconductor structure may be formed as source/drain regions of metal-oxide-semiconductor (MOS) devices.

摘要翻译： 提供一种复合半导体结构及其形成方法。 复合半导体结构包括第一含硅化合物层，其包含选自基本上由锗和碳组成的组的元素; 所述第一含硅化合物层上的硅层，其中所述硅层包含基本上纯的硅; 以及在所述硅层上包含所述元素的第二含硅化合物层。 第一和第二含硅化合物层具有比硅层低的硅浓度。 复合半导体结构可以形成为金属氧化物半导体（MOS）器件的源极/漏极区域。

公开(公告)号：US08253177B2

公开(公告)日：2012-08-28

申请号：US12714001

申请日：2010-02-26

申请人： Ming-Hua Yu ,  Tai-Chun Huang

发明人： Ming-Hua Yu ,  Tai-Chun Huang

IPC分类号： H01L29/78

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833

摘要： A semiconductor device, such as a PMOS or an NMOS transistor, having a stressed channel region is provided. The semiconductor device is formed by recessing the source/drain regions after forming a gate stack. The substrate is removed under the gate stack. Thereafter, an epitaxial layer is formed under the gate stack and in the source/drain regions. The epitaxial layer may be doped in the source/drain regions. In an embodiment, a lower portion of the epitaxial layer and the epitaxial layer under the gate stack may be doped with a conductivity type opposite of the conductivity type of the source/drain regions. In another embodiment of the present invention, a lower portion of the epitaxial layer is left undoped.

摘要翻译： 提供具有应力通道区域的诸如PMOS或NMOS晶体管的半导体器件。 半导体器件通过在形成栅极堆叠之后使源极/漏极区域凹陷来形成。 在栅极堆叠下去除衬底。 此后，在栅叠层和源极/漏极区内形成外延层。 外延层可以掺杂在源极/漏极区域中。 在一个实施例中，外延层的下部和栅叠层下的外延层可以掺杂有与源极/漏极区的导电类型相反的导电类型。 在本发明的另一实施例中，外延层的下部未被掺杂。

公开(公告)号：US06573189B1

公开(公告)日：2003-06-03

申请号：US10044859

申请日：2001-11-07

申请人： Shih-Chi Lin ,  Ming-Hua Yu ,  Szu-An Wu

发明人： Shih-Chi Lin ,  Ming-Hua Yu ,  Szu-An Wu

IPC分类号： H01L21302

CPC分类号： H01L21/0276

摘要： A new method of preventing photoresist footing by forming a silicon oxynitride ARC layer having an oxygen-rich surface is described. An insulating layer is provided on a substrate. A metal layer is deposited overlying the insulating layer. A silicon oxynitride antireflective coating layer having an oxygen-rich surface is deposited overlying the metal layer. A photoresist mask is formed overlying the antireflective coating layer wherein the antireflective coating layer prevents photoresist footing. The antireflective coating layer and the metal layer are etched away where they are not covered by the photoresist mask to complete formation of metal lines in the fabrication of an integrated circuit.

摘要翻译： 描述了通过形成具有富氧表面的氧氮化硅ARC层来防止光致抗蚀剂底脚的新方法。 绝缘层设置在基板上。 沉积在绝缘层上的金属层。 具有富氧表面的氧氮化硅抗反射涂层沉积在金属层上。 形成覆盖抗反射涂层的抗蚀剂掩模，其中抗反射涂层防止光致抗蚀剂底脚。 抗反射涂层和金属层被蚀刻掉，其中它们不被光致抗蚀剂掩模覆盖，以在集成电路的制造中完成金属线的形成。