公开(公告)号：US08344447B2

公开(公告)日：2013-01-01

申请号：US11732889

申请日：2007-04-05

申请人： Hsien-Hsin Lin ,  Weng Chang ,  Chien-Chang Su ,  Kuan-Yu Chen ,  Hsueh-Chang Sung ,  Ming-Hua Yu

发明人： Hsien-Hsin Lin ,  Weng Chang ,  Chien-Chang Su ,  Kuan-Yu Chen ,  Hsueh-Chang Sung ,  Ming-Hua Yu

IPC分类号： H01L29/94

CPC分类号： H01L29/66477 ,  H01L21/02532 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A composite semiconductor structure and method of forming the same are provided. The composite semiconductor structure includes a first silicon-containing compound layer comprising an element selected from the group consisting essentially of germanium and carbon; a silicon layer on the first silicon-containing compound layer, wherein the silicon layer comprises substantially pure silicon; and a second silicon-containing compound layer comprising the element on the silicon layer. The first and the second silicon-containing compound layers have substantially lower silicon concentrations than the silicon layer. The composite semiconductor structure may be formed as source/drain regions of metal-oxide-semiconductor (MOS) devices.

摘要翻译： 提供一种复合半导体结构及其形成方法。 复合半导体结构包括第一含硅化合物层，其包含选自基本上由锗和碳组成的组的元素; 所述第一含硅化合物层上的硅层，其中所述硅层包含基本上纯的硅; 以及在所述硅层上包含所述元素的第二含硅化合物层。 第一和第二含硅化合物层具有比硅层低的硅浓度。 复合半导体结构可以形成为金属氧化物半导体（MOS）器件的源极/漏极区域。

公开(公告)号：US20080246057A1

公开(公告)日：2008-10-09

申请号：US11732889

申请日：2007-04-05

申请人： Hsien-Hsin Lin ,  Weng Chang ,  Chien-Chang Su ,  Kuan-Yu Chen ,  Hsueh-Chang Sung ,  Ming-Hua Yu

发明人： Hsien-Hsin Lin ,  Weng Chang ,  Chien-Chang Su ,  Kuan-Yu Chen ,  Hsueh-Chang Sung ,  Ming-Hua Yu

IPC分类号： H01L29/78

CPC分类号： H01L29/66477 ,  H01L21/02532 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A composite semiconductor structure and method of forming the same are provided. The composite semiconductor structure includes a first silicon-containing compound layer comprising an element selected from the group consisting essentially of germanium and carbon; a silicon layer on the first silicon-containing compound layer, wherein the silicon layer comprises substantially pure silicon; and a second silicon-containing compound layer comprising the element on the silicon layer. The first and the second silicon-containing compound layers have substantially lower silicon concentrations than the silicon layer. The composite semiconductor structure may be formed as source/drain regions of metal-oxide-semiconductor (MOS) devices.

摘要翻译： 提供一种复合半导体结构及其形成方法。 复合半导体结构包括第一含硅化合物层，其包含选自基本上由锗和碳组成的组的元素; 所述第一含硅化合物层上的硅层，其中所述硅层包含基本上纯的硅; 以及在所述硅层上包含所述元素的第二含硅化合物层。 第一和第二含硅化合物层具有比硅层低的硅浓度。 复合半导体结构可以形成为金属氧化物半导体（MOS）器件的源极/漏极区域。

公开(公告)号：US08258588B2

公开(公告)日：2012-09-04

申请号：US12757241

申请日：2010-04-09

申请人： Yu Chao Lin ,  Jr Jung Lin ,  Yih-Ann Lin ,  Jih-Jse Lin ,  Chao-Cheng Chen ,  Ryan Chia-Jen Chen ,  Weng Chang

发明人： Yu Chao Lin ,  Jr Jung Lin ,  Yih-Ann Lin ,  Jih-Jse Lin ,  Chao-Cheng Chen ,  Ryan Chia-Jen Chen ,  Weng Chang

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L29/4983 ,  H01L29/6656

摘要： An exemplary structure for a gate structure of a field effect transistor comprises a gate electrode; a gate insulator under the gate electrode having footing regions on opposing sides of the gate electrode; and a sealing layer on sidewalls of the gate structure, wherein a thickness of lower portion of the sealing layer overlying the footing regions is less than a thickness of upper portion of the sealing layer on sidewalls of the gate electrode, whereby the field effect transistor made has almost no recess in the substrate surface.

摘要翻译： 场效应晶体管的栅极结构的示例性结构包括栅电极; 栅电极下方的栅极绝缘体，在栅电极的相对侧具有基极区域; 以及在所述栅极结构的侧壁上的密封层，其中覆盖所述基底区域的所述密封层的下部的厚度小于所述栅极电极的侧壁上的所述密封层的上部的厚度，由此所述场效应晶体管 在基板表面几乎没有凹陷。

公开(公告)号：US20080308899A1

公开(公告)日：2008-12-18

申请号：US11763566

申请日：2007-06-15

申请人： Yu-Lien Huang ,  Yi-Chen Huang ,  Jim Cy Huang ,  Weng Chang ,  Hun-Jan Tao

发明人： Yu-Lien Huang ,  Yi-Chen Huang ,  Jim Cy Huang ,  Weng Chang ,  Hun-Jan Tao

IPC分类号： H01L29/06 ,  H01L29/00

CPC分类号： H01L21/823425 ,  H01L21/823468 ,  Y10S438/981

摘要： Provided is a semiconductor device including a substrate. A gate formed on the substrate. The gate includes a sidewall. A spacer formed on the substrate and adjacent the sidewall of the gate. The spacer has a substantially triangular geometry. A contact etch stop layer (CESL) is formed on the first gate and the first spacer. The thickness of the CESL to the width of the first spacer is between approximately 0.625 and 16.

摘要翻译： 提供了包括基板的半导体器件。 形成在基板上的栅极。 门包括侧壁。 在衬底上形成并且邻近门的侧壁的间隔物。 间隔件具有基本上三角形的几何形状。 在第一栅极和第一间隔物上形成接触蚀刻停止层（CESL）。 CESL的厚度与第一间隔件的宽度在大约0.625和16之间。

公开(公告)号：US20080242108A1

公开(公告)日：2008-10-02

申请号：US11730551

申请日：2007-04-02

申请人： Weng Chang ,  Fong-Yu Yen ,  Hun-Jan Tao ,  Mong-Song Liang

发明人： Weng Chang ,  Fong-Yu Yen ,  Hun-Jan Tao ,  Mong-Song Liang

IPC分类号： H01L21/46

CPC分类号： H01L21/28079 ,  H01L21/28088 ,  H01L21/67207

摘要： A method for fabricating a semiconductor device is disclosed. The method includes providing a first chamber and a second chamber. The first chamber and the second chamber are connected by a pressure differential unit, for depositing a metallic film over a substrate in the first chamber, transferring the substrate to the second chamber via the pressure differential unit without exposing the substrate to the ambient environment, and depositing a silicon-containing film on the metallic film in the second chamber.

摘要翻译： 公开了一种制造半导体器件的方法。 该方法包括提供第一室和第二室。 第一室和第二室通过压力差单元连接，用于在第一室中的基板上沉积金属膜，经由压差单元将衬底转移到第二室，而不将衬底暴露于周围环境;以及 在第二室中的金属膜上沉积含硅膜。

公开(公告)号：US20050245100A1

公开(公告)日：2005-11-03

申请号：US10835788

申请日：2004-04-30

申请人： Zhen-Cheng Wu ,  Bi-Troug Chen ,  Weng Chang ,  Syun-Ming Jang ,  Su-Horng Lin

发明人： Zhen-Cheng Wu ,  Bi-Troug Chen ,  Weng Chang ,  Syun-Ming Jang ,  Su-Horng Lin

IPC分类号： H01L21/306 ,  H01L21/314 ,  H01L21/316 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/31633 ,  H01L21/02046 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/3148 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76832

摘要： A method of forming a SiCOH etch stop layer in a copper damascene process is described. A substrate with an exposed metal layer is treated with H2 or NH3 plasma to remove metal oxides. Trimethylsilane is flowed into a chamber with no RF power at about 350° C. to form at least a monolayer on the exposed metal layer. The SiCOH layer is formed by a PECVD process including trimethylsilane and CO2 source gases. Optionally, a composite SiCOH layer comprised of a low compressive stress layer on a high compressive stress layer is formed on the substrate. A conventional damascene sequence is then used to form a second metal layer on the exposed metal layer. Via Rc stability is improved and a lower leakage current is achieved with the trimethylsilane passivation layer. A composite SiCOH etch stop layer provides improved stress migration resistance compared to a single low stress SiCOH layer.

摘要翻译： 描述了在铜镶嵌工艺中形成SiCOH蚀刻停止层的方法。 具有暴露的金属层的衬底用H 2 N 3或NH 3 3等离子体处理以除去金属氧化物。 三甲基硅烷在约350℃下流入没有RF功率的室，以在暴露的金属层上形成至少单层。 SiCOH层通过包括三甲基硅烷和CO 2原子气体的PECVD工艺形成。 任选地，在基底上形成由高压缩应力层上的低压应力层构成的复合SiCOH层。 然后使用常规的镶嵌序列在暴露的金属层上形成第二金属层。 通过Rc稳定性提高，并且用三甲基硅烷钝化层实现较低的漏电流。 与单个低应力SiCOH层相比，复合SiCOH蚀刻停止层提供改进的应力迁移阻力。

公开(公告)号：US20050050708A1

公开(公告)日：2005-03-10

申请号：US10656586

申请日：2003-09-04

申请人： Yu-Lien Huang ,  Weng Chang ,  Syun-Ming Jang ,  Mong Song Liang

发明人： Yu-Lien Huang ,  Weng Chang ,  Syun-Ming Jang ,  Mong Song Liang

IPC分类号： B21D39/03 ,  B23P11/00 ,  C23C16/44

CPC分类号： C23C16/45565 ,  C23C16/4401 ,  Y10T29/49826 ,  Y10T29/49947

摘要： A novel embedded fastener apparatus and method for fastening components to the interior of a process chamber of a semiconductor fabrication apparatus. In one embodiment, an apparatus having a showerhead or gas distribution plate which is mounted to the interior of the process chamber using multiple fasteners which are embedded in respective fastener openings in the showerhead. In another embodiment, an apparatus having a showerhead which is mounted to the interior of the process chamber using multiple exterior fasteners which extend into the showerhead through the walls of the process chamber. Accordingly, the regions of the showerhead which surround the fasteners are physically separated from the interior of the process chamber.

摘要翻译： 一种用于将部件固定到半导体制造装置的处理室的内部的新颖的嵌入式紧固装置和方法。 在一个实施例中，一种具有喷头或气体分配板的装置，其使用嵌入在喷头中的相应紧固件开口中的多个紧固件安装到处理室的内部。 在另一个实施例中，一种具有喷头的装置，其使用多个外部紧固件安装到处理室的内部，多个外部紧固件通过处理室的壁延伸到喷头中。 因此，围绕紧固件的喷头的区域在物理上与处理室的内部分离。

公开(公告)号：US06271138B1

公开(公告)日：2001-08-07

申请号：US09405058

申请日：1999-09-27

申请人： Weng Chang ,  Syun-Ming Jang

发明人： Weng Chang ,  Syun-Ming Jang

IPC分类号： H01L21302

CPC分类号： H01L21/31053

摘要： A chemical mechanical polish (CMP) planarizing method for forming a chemical mechanical polish (CMP) planarized microelectronic layer within a microelectronic fabrication employs first a substrate. There is then formed over the substrate a microelectronic layer. There is then planarized, while employing a chemical mechanical polish (CMP) planarizing method, the microelectronic layer to form a chemical mechanical polish (CMP) planarized microelectronic layer. Within the method, the microelectronic layer when formed over the substrate is formed with a thickness variation which compensates for a chemical mechanical polish (CM) rate non-uniformity when forming while employing the chemical mechanical polish (CMP) planarizing method the chemical mechanical polish (CMP) planarized microelectronic layer from the microelectronic layer.

摘要翻译： 用于在微电子制造中形成化学机械抛光（CMP）平面化微电子层的化学机械抛光（CMP）平面化方法首先使用衬底。 然后在衬底上形成微电子层。 然后平面化，同时采用化学机械抛光（CMP）平面化方法，微电子层形成化学机械抛光（CMP）平面化微电子层。 在该方法中，当形成在衬底上的微电子层形成厚度变化，其在成形时补偿化学机械抛光（CM）速率不均匀性，同时使用化学机械抛光（CMP）平面化方法化学机械抛光 CMP）平面化微电子层。

公开(公告)号：US5514350A

公开(公告)日：1996-05-07

申请号：US231026

申请日：1994-04-22

申请人： Bernard H. Kear ,  Weng Chang ,  Ganesh Skandan ,  Horst W. Hahn

发明人： Bernard H. Kear ,  Weng Chang ,  Ganesh Skandan ,  Horst W. Hahn

IPC分类号： B01J12/02 ,  B01J19/18 ,  B01J19/24 ,  C01B21/068 ,  C01B21/082 ,  C01B31/36 ,  C04B35/626 ,  C30B25/00 ,  F25B29/00

CPC分类号： B82Y30/00 ,  B01J12/02 ,  B01J19/18 ,  B01J19/2415 ,  C01B21/068 ,  C01B21/0828 ,  C01B31/36 ,  C04B35/626 ,  C30B25/005 ,  C30B29/36 ,  C30B29/38 ,  B01J2219/00085 ,  B01J2219/00094 ,  B01J2219/00162 ,  B01J2219/00164 ,  C01P2002/72 ,  C01P2004/10 ,  C01P2004/50 ,  C01P2004/64 ,  C01P2006/10 ,  C01P2006/12 ,  C01P2006/60 ,  C01P2006/80 ,  F02B2275/14 ,  Y02T10/123 ,  Y10S977/776 ,  Y10S977/835 ,  Y10S977/84

摘要： An apparatus of forming non-agglomerated nanostructured ceramic (n-ceramic) powders from metalorganic precursors combines rapid thermal decomposition of a precursor/carrier gas stream in a hot tubular reactor with rapid condensation of the product particles on a cold substrate under a reduced inert gas pressure of 1-50 mbar. A wide variety of metalorganic precursors is available. The apparatus is particularly suitable for formation of n-SiC.sub.x N.sub.y powders from hexamethyl-disilizane or the formation of n-ZrO.sub.x C.sub.y powders from zirconium tertiary butoxide. The n-SiC.sub.x N.sub.y compounds can be further reacted to form SiC or Si.sub.3 N.sub.4 whiskers, individually or in random-weave form, by heating in a hydrogen or ammonia atmosphere. The non-agglomerated n-ceramic powders form uniformly dense powder compacts by cold pressing which can be sintered to theoretical density at temperatures as low as 0.5 Tm. By appropriate choice of precursor compound and carrier gas, this apparatus can be used to produce nanoosized powders of almost any desired material, including metals, intermetallics, semiconductors, superconductors, ferro-electrics, optically active materials and magnetic materials, as well as their composites.

摘要翻译： 从金属有机前体形成非凝聚的纳米结构陶瓷（n-陶瓷）粉末的装置将热管式反应器中的前体/载气流的快速热分解与产物颗粒在还原惰性气体下在冷的基底上快速冷凝 压力为1-50毫巴。 有各种各样的金属有机前体可用。 该装置特别适用于从六甲基二硅氮烷形成n-SiCxNy粉末或由叔丁醇锆形成正ZrOxCy粉末。 可以通过在氢气或氨气氛中加热，使n-SiC x N y化合物单独地或以无规方式形成SiC或Si 3 N 4晶须。 未凝聚的n型陶瓷粉末通过冷压形成均匀致密的粉末压坯，其可以在低至0.5Tm的温度下烧结至理论密度。 通过适当选择前体化合物和载气，该装置可用于生产几乎任何所需材料的纳米尺寸粉末，包括金属，金属间化合物，半导体，超导体，铁电，光学活性材料和磁性材料，以及它们的复合材料 。

公开(公告)号：US07119404B2

公开(公告)日：2006-10-10

申请号：US10849689

申请日：2004-05-19

申请人： Cheng-Hung Chang ,  Weng Chang ,  Chu-Yun Fu

发明人： Cheng-Hung Chang ,  Weng Chang ,  Chu-Yun Fu

IPC分类号： H01L31/62 ,  H01L21/8238

CPC分类号： H01L29/7845 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7846

摘要： Strained channel transistors including a PMOS and NMOS device pair to improve an NMOS device performance without substantially degrading PMOS device performance and method for forming the same, the method including providing a semiconductor substrate; forming strained shallow trench isolation regions in the semiconductor substrate; forming PMOS and NMOS devices on the semiconductor substrate including doped source and drain regions; forming a tensile strained contact etching stop layer (CESL) over the PMOS and NMOS devices; and, forming a tensile strained dielectric insulating layer over the CESL layer.

摘要翻译： 包括PMOS和NMOS器件对的应变沟道晶体管，以改善NMOS器件性能而不会使PMOS器件性能基本上降低，并且用于形成PMOS器件性能的方法，所述方法包括提供半导体衬底; 在半导体衬底中形成应变浅沟槽隔离区; 在包括掺杂源极和漏极区域的半导体衬底上形成PMOS和NMOS器件; 在PMOS和NMOS器件上形成拉伸应变接触蚀刻停止层（CESL）; 并在CESL层上形成拉伸应变电介质绝缘层。