公开(公告)号：US5334930A

公开(公告)日：1994-08-02

申请号：US882476

申请日：1992-05-13

申请人： Akira Onodera ,  Koichi Yamazaki

发明人： Akira Onodera ,  Koichi Yamazaki

IPC分类号： G11B20/10 ,  G01R19/04 ,  H03K5/1532 ,  H03K5/19

CPC分类号： H03K5/1532 ,  G01R19/04

摘要： A peak detection circuit accurately detects peaks even if a noise component is included in the input signal. The peak detection circuit includes: a differentiating circuit which produces a differentiated signal of an input signal, a peak hold circuit which produces a peak value envelope of an output of said differentiating circuit, and a first comparator which compares an output of said differentiating circuit and a reference signal formed on the basis of an output of said peak hold circuit, and which detects when said input signal falls below said reference signal A second comparator detects a portion which exceeds an output of said differentiating circuit A flip-flop produces a signal which rises in accordance with an output of said second comparator and falls in accordance with an output of said first comparator, thereby to form a signal representing a peak by the rise of an output of said flip-flop.

摘要翻译： 峰值检测电路即使噪声分量包含在输入信号中也能精确地检测峰值。 峰值检测电路包括：产生输入信号的微分信号的微分电路，产生所述微分电路的输出的峰值包络的峰值保持电路，以及将所述微分电路的输出和 基于所述峰值保持电路的输出形成的参考信号，并且检测所述输入信号何时下降到所述参考信号A以下的位置。第二比较器检测到超过所述微分电路A的输出的部分。触发器产生一个信号， 根据所述第二比较器的输出上升，并且根据所述第一比较器的输出而下降，从而通过所述触发器的输出的上升形成表示峰值的信号。

公开(公告)号：US5315168A

公开(公告)日：1994-05-24

申请号：US54035

申请日：1993-04-28

申请人： David E. Norton, Jr.

发明人： David E. Norton, Jr.

IPC分类号： G01R19/04 ,  H03K5/1532 ,  H03K5/24

CPC分类号： H03K5/1532 ,  G01R19/04

摘要： A peak hold circuit includes an operational amplifier in a continually closed feedback loop and a peak hold capacitor with a discharge path. An input signal is received at a first input of the amplifier, and the output of the amplifier is fed to a first transistor then fed back therefrom to a second input of the amplifier. A current sink is coupled to the first transistor for drawing a current therefrom so that the feedback signal is continually provided to the second amplifier input, ensuring that the amplifier is in a continually closed feedback loop. The output of the amplifier is supplied to the peak hold capacitor through a second transistor.

摘要翻译： 峰值保持电路包括连续闭合反馈回路中的运算放大器和具有放电路径的峰值保持电容器。 在放大器的第一输入处接收输入信号，并且将放大器的输出馈送到第一晶体管，然后从第一晶体管反馈到放大器的第二输入端。 电流吸收器耦合到第一晶体管以从其中抽出电流，使得反馈信号被连续提供给第二放大器输入，确保放大器处于连续闭合的反馈回路中。 放大器的输出通过第二晶体管提供给峰值保持电容。

公开(公告)号：US5300825A

公开(公告)日：1994-04-05

申请号：US933713

申请日：1992-08-24

申请人： Yoshiji Inoue ,  Takehiko Umeyama

发明人： Yoshiji Inoue ,  Takehiko Umeyama

IPC分类号： G01R19/04 ,  G01R29/00 ,  G11B5/09 ,  H03K5/08 ,  H03K5/1532 ,  H03K5/153

CPC分类号： H03K5/1532 ,  H03K5/08

摘要： This invention provides a peak signal detecting device by which a peak of an input signal can be accurately detected even if a noise is caused. A level slice circuit (3) outputs a level slice signal S3 which turns to High/Low depending upon whether an absolute value of a reading signal S0 is more/less than a threshold value VT1. A level slice circuit (5) outputs a level slice signal S5 which turns to High/Low depending upon whether an absolute value of a differentiated signal S1 is more/less than a threshold value VT2. A delay circuit (6) delays a leading edge of the level slice signal S5 for a period T1 and its trailing edge for a period T2 to produce a delay signal S6. At this time, this process is cancelled when the High level of the level slice signal S5 is less than T1. A gate circuit (4) outputs a conjunction of a zero cross signal S2, level slice signal S3 and delay signal S6 as a gate signal S4' (peak detecting signal).

摘要翻译： 本发明提供一种峰值信号检测装置，通过该装置，即使产生噪声，也可以准确地检测输入信号的峰值。 电平切片电路（3）根据读取信号S0的绝对值是否大于阈值VT1输出电平切片信号S3，该电平切片信号S3变为高/低。 电平切片电路（5）输出根据微分信号S1的绝对值是否大于/小于阈值VT2而变为高/低的电平切片信号S5。 延迟电路（6）将电平切片信号S5的前沿延迟一段时间T1及其后沿一段时间T2以产生延迟信号S6。 此时，当电平切片信号S5的高电平小于T1时，该处理被取消。 门电路（4）输出零交叉信号S2，电平切片信号S3和延迟信号S6的结合作为门信号S4'（峰值检测信号）。

公开(公告)号：US5231397A

公开(公告)日：1993-07-27

申请号：US770922

申请日：1991-10-04

申请人： Frank Ridkosil

发明人： Frank Ridkosil

IPC分类号： H03K5/1532 ,  H03M1/12 ,  H04K1/00 ,  H04L7/027 ,  H04L27/06

CPC分类号： H04L7/027 ,  H03K5/1532 ,  H03M1/1275 ,  H04K1/00 ,  H04L27/06

摘要： A circuit and method for representing in digital form information about the time and amplitude characteristic of a time-varying input signal. The time-varying input signal is delayed and the magnitudes of the time-varying input signal and its delayed version are compared to produce a digital signal representing the time characteristic of the input signal in the form of a transition in a digital output signal each time the magnitudes of the compared signals have a predetermined relationship. The predetermined relationship may be a condition of approximate equality or when the magnitude of the larger of the compared signals becomes less than the magnitude of the smaller of the compared signals. The invention also includes a circuit for outputting a digital representation of the amplitude of the time-varying input signal for each transition of said digital output signal. The disclosed circuits thus provide separate digital representations of the time and amplitude of each peak and valley of an analog or other time-varying input signal. The invention also includes an application of the analog-to-digital converter in a pitch tracking circuit.

摘要翻译： 用于以数字方式表示关于时变输入信号的时间和幅度特性的信息的电路和方法。 时变输入信号被延迟并且时变输入信号及其延迟版本的幅度被比较以产生表示每次数字输出信号中的转变形式的输入信号的时间特性的数字信号 比较信号的幅度具有预定的关系。 预定关系可以是近似相等的条件，或者当比较的信号的较大者的大小变得小于比较的信号的较小者的大小时。 本发明还包括用于输出对于所述数字输出信号的每个转换的时变输入信号的振幅的数字表示的电路。 所公开的电路因此提供模拟或其他时变输入信号的每个峰谷的时间和幅度的分开的数字表示。 本发明还包括模数转换器在音调跟踪电路中的应用。

公开(公告)号：US4979189A

公开(公告)日：1990-12-18

申请号：US395967

申请日：1989-08-18

申请人： Donald T. Wile

发明人： Donald T. Wile

IPC分类号： G11B20/14 ,  G11B20/10 ,  G11B20/12 ,  G11B20/18 ,  H03K5/1532

CPC分类号： H03K5/1532 ,  G11B20/10009 ,  G11B20/1258

摘要： A novel self-timing qualification channel structure is taught, suitable for use in detecting data from a magnetic disk or other storage medium. A timing comparator is used in addition to a hysteresis comparator in order to detect when the true peak of the input signal is about to occur. The timing comparator output determines when signal qualification by the hysteresis comparator is to occur. The timing comparator only allows signal qualification to occur just prior to the true peak in the input signal. Because of this, the risk of falsely detecting off track noise or noise in the shoulder region is greatly reduced. In one embodiment, the timing comparator operates without the need for additional external components by utilizing the existing channel filter. Thus, the channel filter serves two purposes: to filter the channel input signal prior to detection and to provide delay for the timing comparator. The detector of this invention is ideally suited for detecting data from a constant density recording environment where a multiple data rates are encountered. The improved immunity to off track noise allows track density to be increased, thereby increasing the storage capacity of the disk.

公开(公告)号：US4916673A

公开(公告)日：1990-04-10

申请号：US212555

申请日：1988-06-28

申请人： Steven A. Morris ,  Houston B. Mount

发明人： Steven A. Morris ,  Houston B. Mount

IPC分类号： G01V1/26 ,  H03K5/1532

CPC分类号： G01V1/26 ,  H03K5/1532

摘要： A method and apparatus for processing a signal generated by a borehole scanning system of the type in which periodic electrical firing pulses initiate a plurality of corresponding acoustic energy pulses which are transmitted from the central portion of the borehole toward the borehole wall in a plurality of radial directions and at a plurality of different depths, thereby generating reflected acoustic pulses which are detected and converted to electrical pulses. The electrical pulse is periodically sampled with each sample level being converted to a digital number. A counter initiates counting in response to the firing pulse preceding the sample electrical pulse. Upon detection of the peak of the electrical pulse, the counter count is stored. Upon detection of the electrical pulse again falling below a preselected level, the count is again stored. Then the time midway between the two stored counts is determined.

摘要翻译： 一种用于处理由钻孔扫描系统产生的信号的方法和装置，其中周期性电击脉冲启动多个对应的声能脉冲，其从钻孔的中心部分向多个径向的钻孔壁传送 方向和多个不同深度，从而产生被检测并转换成电脉冲的反射声脉冲。 电脉冲周期性地被采样，每个采样电平被转换成数字数字。 计数器响应于采样电脉冲之前的点火脉冲启动计数。 当检测到电脉冲的峰值时，计数器计数被存储。 当检测到电脉冲再次低于预选电平时，计数再次被存储。 然后确定两个存储的计数之间的时间。

公开(公告)号：US4806792A

公开(公告)日：1989-02-21

申请号：US069407

申请日：1987-07-01

申请人： Elmer Simmons

发明人： Elmer Simmons

IPC分类号： G11B20/10 ,  H03K5/02 ,  H03K5/1532 ,  H03K5/24 ,  H03K5/22

CPC分类号： G11B20/10 ,  H03K5/02 ,  H03K5/1532 ,  H03K5/2418

摘要： A new differential amplifier circuit including two current mode logic circuits, each comprising a pair of transistors whose emitters are connected to a common current source. The differential amplifier circuit receives three input signals, with a transistor in both of the current mode logic circuits being controlled by one of the input signals. The collector outputs of the two transistors controlled by a single input signal are connected together, and the collector outputs of the two transistors controlled by the other two input signals are also connected together, in both cases to form summing junctions. The summing junctions are connected to an output buffer to generate a pair of signals constituting differential output signals.

摘要翻译： 一种新的差分放大器电路，包括两个电流模式逻辑电路，每个电路都包括一对晶体管，其发射极连接到公共电流源。 差分放大器电路接收三个输入信号，两个电流模式逻辑电路中的晶体管由输入信号之一控制。 由单个输入信号控制的两个晶体管的集电极输出连接在一起，并且由其它两个输入信号控制的两个晶体管的集电极输出也连接在一起，在这两种情况下形成相加结。 求和结连接到输出缓冲器以产生构成差分输出信号的一对信号。

公开(公告)号：US4736163A

公开(公告)日：1988-04-05

申请号：US756140

申请日：1985-07-17

申请人： Petrus J. Berkhout ,  Johan M. Rijnsburger

发明人： Petrus J. Berkhout ,  Johan M. Rijnsburger

IPC分类号： H03K5/1252 ,  G01R19/04 ,  G01R19/165 ,  H03G3/34 ,  H03H17/00 ,  H03K5/04 ,  H03K5/153 ,  H03K5/1532 ,  H04B1/10 ,  H03B1/00 ,  H03K5/22

CPC分类号： H03G3/345 ,  G01R19/04 ,  G01R19/16585 ,  H03K5/04 ,  H03K5/153

摘要： The circuit arrangement for detecting pulse-shaped interferences in an electrical signal comprises an input (7), a high-pass filter (8) having a cut-off frequency lying between 40 Hz and 1000 Hz, one or two signal paths (25, 25') and an output (5). A signal path (25) comprises a peak detector (10), a device (11) for determining a running average value, of its input signal, a delay unit (12) and a comparator (15). The output of the peak detector (10) is coupled via the device (11) for determining a running average value to a first input (13) of the comparator and via the delay unit (12) to a second input (14) of the comparator. The comparator compares the delayed output signal of the peak detector with the output signal of the device for determining the running average value and supplies an output signal to its output (16) if the output signal of the peak detector is larger than a times the output signal of the device for determining the running average value, where it holds that a>1. With this circuit arrangement, a more satisfactory detection of pulse-shaped interferences is attained (FIG. 3). The circuit arrangement may be used, for example, as a detector circuit in an arrangement for detecting and suppressing pulse-shaped interferences. (FIG. 1).

摘要翻译： 用于检测电信号中的脉冲形干扰的电路装置包括输入（7），具有位于40Hz和1000Hz之间的截止频率的高通滤波器（8），一个或两个信号路径（25， 25'）和输出（5）。 信号路径（25）包括峰值检测器（10），用于确定其输入信号的运行平均值的装置（11），延迟单元（12）和比较器（15）。 峰值检测器（10）的输出经由设备（11）耦合，用于确定比较器的第一输入端（13）的运行平均值，并且经由延迟单元（12）到达第二输入端 比较器。 比较器将峰值检测器的延迟输出信号与器件的输出信号进行比较，以确定运行平均值，并且如果峰值检测器的输出信号大于输出的输出信号，则将输出信号提供给其输出（16） 用于确定运行平均值的设备的信号，其中a> 1。 利用该电路装置，可获得令人满意的脉冲形干扰检测（图3）。 电路装置可以用作例如用于检测和抑制脉冲形干扰的装置中的检测器电路。 （图。1）。

公开(公告)号：US4697098A

公开(公告)日：1987-09-29

申请号：US743037

申请日：1985-06-10

申请人： Robert L. Cloke

发明人： Robert L. Cloke

IPC分类号： G11B5/09 ,  G01R29/02 ,  G11B20/22 ,  H03K5/1532 ,  H03K5/153

CPC分类号： H03K5/1532 ,  G01R29/02

摘要： A gate generator useful for validating readout signals incorporates three channels, including differentiators and threshold comparators, and a logic circuit coupled to the output circuits of the channels for passing valid readout signals. The output signals of the comparators and of detected zero crossings derived from a differentiated signal are fed to the logic circuit for processing.

摘要翻译： 用于验证读出信号的门极发生器包括三个通道，包括微分器和阈值比较器，以及耦合到通道的输出电路的逻辑电路，用于传递有效的读出信号。 比较器的输出信号和从微分信号导出的检测到的过零点被馈送到逻辑电路进行处理。

公开(公告)号：US4480276A

公开(公告)日：1984-10-30

申请号：US402507

申请日：1982-07-28

申请人： Robert M. Batey ,  James D. Becker

发明人： Robert M. Batey ,  James D. Becker

IPC分类号： H03K5/01 ,  G11B5/09 ,  G11B20/10 ,  G11B20/24 ,  H03K5/1532

CPC分类号： H03K5/1532 ,  G11B20/10009 ,  G11B20/24

摘要： An apparatus is disclosed for detecting the peaks of a signal recorded on a magnetic storage medium. An absolute value circuit is used to generate an output that is approximately equivalent to the mathematical absolute value of the raw signal input from the storage medium. The absolute value signal is then coupled to both a differentiator circuit and a noise rejection comparator circuit. A second comparator which detects the zero voltage crossings of the differentiator circuit is enabled and disabled by the output from the noise rejection comparator so that transitions of opposite polarity are produced, corresponding to the peaks and positive going reference level crossings of the raw signal input, while noise on the raw signal input below a qualification level established by the noise rejection comparator circuit is rejected. The output of the second comparator is then coupled to a monostable multivibrator which produces digital pulses of a desired period which correspond to the peaks of the signal record on the magnetic storage medium.

摘要翻译： 公开了一种用于检测记录在磁存储介质上的信号的峰值的装置。 绝对值电路用于产生大致相当于从存储介质输入的原始信号的数学绝对值的输出。 然后将绝对值信号耦合到微分电路和噪声抑制比较器电路两者。 检测微分电路的零电压交叉的第二比较器通过来自噪声抑制比较器的输出而被使能和禁止，使得对应于原始信号输入的峰值和正向参考电平交叉产生相反极性的转变， 而由噪声抑制比较器电路建立的低于资格级别的原始信号输入端的噪声被拒绝。 然后将第二比较器的输出耦合到单稳态多谐振荡器，其产生对应于磁存储介质上的信号记录的峰值的期望周期的数字脉冲。